[ARM] Enable Cortex-M23 and Cortex-M33 support.

[sanwou01]

Summary

Add both cores to the target parser and TableGen. Tests that eabi
attributes are set correctly for both cores. Additionally, test the
absence and presence of MOVT in Cortex-M23 and Cortex-M33, respectively.

[sanwou01]

Depends on https://reviews.llvm.org/D29020 for cortex-m23.ll to pass. FYI, I do not have commit access.

[rengolin]

This patch has too many issues in one:

1. Adding new M cores to the target parser. The testing has to be done in the unit-test (as you've done). Check.

2. Adding new M cores to TableGen. Testing needs to be done by adding the new core to existing tests and using the appropriate CHECK lines (not adding new ones).

3. Adding a test to tail call, which should belong to D29020.

4. Heavily modifying the SW/HWDIV test, even though the hardware description you added in TableGen has no mention of special DIV features that would separate it from the other M cores.

I suggest you:

A. Keep the Target Parser and the TableGen changes here, but instead of modifying existing tests, just add new RUN lines to them where other M cores are tested and reuse the existing CHECK lines.

B. Move the tail-call test to D29020.

cheers,
--renato

test/CodeGen/ARM/cortex-m23.ll

1

This test is completely different to the patch, I'm not sure why you moved it here.

test/CodeGen/ARM/div.ll

2

Too many check lines increase the risk of tests being ignored, especially when you just rename them below, instead of adding new ones.

[sanwou01]

In D29073#654679, @rengolin wrote:

This patch has too many issues in one:

1. Adding new M cores to the target parser. The testing has to be done in the unit-test (as you've done). Check.

2. Adding new M cores to TableGen. Testing needs to be done by adding the new core to existing tests and using the appropriate CHECK lines (not adding new ones).

I see, I'll get on that.

3. Adding a test to tail call, which should belong to D29020.

Moved, sorry about that.

4. Heavily modifying the SW/HWDIV test, even though the hardware description you added in TableGen has no mention of special DIV features that would separate it from the other M cores.

The cortex-m23 is sufficiently different from the other processors checked in this file that the extra CHECK lines were necessary. I can add a new file to test HWDIV on Thumb 1. I'll submit a separate patch for that.

I suggest you:

A. Keep the Target Parser and the TableGen changes here, but instead of modifying existing tests, just add new RUN lines to them where other M cores are tested and reuse the existing CHECK lines.

B. Move the tail-call test to D29020.

Thanks, will do.

[rengolin]

In D29073#654796, @sanwou01 wrote:

4. Heavily modifying the SW/HWDIV test, even though the hardware description you added in TableGen has no mention of special DIV features that would separate it from the other M cores.

The cortex-m23 is sufficiently different from the other processors checked in this file that the extra CHECK lines were necessary. I can add a new file to test HWDIV on Thumb 1. I'll submit a separate patch for that.

Right, extra checks are ok, changing the old check is risky. If there's too much bloat, you can split the test or just duplicate some of the CHECK lines.

The Thumb1 HWDIV test is probably best on its own.

cheers,
--renato

[sanwou01]

Updated patch as per @rengolin's suggestions.

[rengolin]

LGTM. Thanks!

include/llvm/Support/ARMTargetParser.def

ARM_CPU_NAME("cortex-r7", AK_ARMV7R, FK_VFPV3_D16_FP16, false,
              (ARM::AEK_MP | ARM::AEK_HWDIVARM))
 ARM_CPU_NAME("cortex-r8", AK_ARMV7R, FK_VFPV3_D16_FP16, false,
              (ARM::AEK_MP | ARM::AEK_HWDIVARM))
 ARM_CPU_NAME("cortex-r52", AK_ARMV8R, FK_NEON_FP_ARMV8, true, ARM::AEK_NONE)
 ARM_CPU_NAME("sc300", AK_ARMV7M, FK_NONE, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m3", AK_ARMV7M, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m4", AK_ARMV7EM, FK_FPV4_SP_D16, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-m7", AK_ARMV7EM, FK_FPV5_D16, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-m23", AK_ARMV8MBaseline, FK_NONE, false, ARM::AEK_NONE)
+ARM_CPU_NAME("cortex-m33", AK_ARMV8MMainline, FK_FPV5_SP_D16, false, ARM::AEK_DSP)
 ARM_CPU_NAME("cortex-a32", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)

lib/Target/ARM/ARM.td

def : ProcNoItin<"cortex-m4",                           [ARMv7em,
                                                          FeatureVFP4,
                                                          FeatureVFPOnlySP,
                                                          FeatureD16]>;
 
 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
                                                          FeatureFPARMv8,
                                                          FeatureD16]>;
 
+def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
+                                                         FeatureNoMovt]>;
+
+def : ProcNoItin<"cortex-m33",                          [ARMv8mMainline,
+                                                         FeatureDSP,
+                                                         FeatureT2XtPk,
+                                                         FeatureFPARMv8,
+                                                         FeatureD16,
+                                                         FeatureVFPOnlySP]>;
+
 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
                                                          FeatureHWDiv,

test/CodeGen/ARM/cortex-m23.ll

+; RUN: llc %s -o - -mtriple=thumbv8m.base -mcpu=cortex-m23 | FileCheck %s
+
+define i32 @test(i32 %Enum_Val_Par, i32* nocapture %Enum_Ref_Par) {
+entry:
+  %call = tail call i32 @Func_3(i32 %Enum_Val_Par)
+  %tobool = icmp ne i32 %call, 0
+  %cond = select i1 %tobool, i32 3, i32 %Enum_Val_Par
+  store i32 %cond, i32* %Enum_Ref_Par, align 4
+; CHECK: cbnz
+; CHECK-NOT: cmp
+; CHECK-NOT: bne
+
+  %tail = tail call i32 @Proc_7(i32 10, i32 %Enum_Val_Par, i32* %Enum_Ref_Par)
+  ret i32 undef
+; CHECK: bl Proc_7
+; CHECK-NOT: b Proc_7
+}
+
+define i32 @test2(i32 %Enum_Val_Par, i32* nocapture %Enum_Ref_Par) {
+entry:
+  %tobool = icmp ne i32 %Enum_Val_Par, 0
+  %cond = select i1 %tobool, i32 3, i32 %Enum_Val_Par
+  store i32 %cond, i32* %Enum_Ref_Par, align 4
+; CHECK: cbnz
+; CHECK-NOT: cmp
+; CHECK-NOT: bne
+
+  %tail = tail call i32 @Proc_7(i32 10, i32 %Enum_Val_Par, i32* %Enum_Ref_Par)
+  ret i32 undef
+; CHECK: b Proc_7
+; CHECK-NOT: bl
+}
+
+declare i32 @Proc_7(i32, i32, i32*)
+
+declare i32 @Func_3(i32)
+

test/CodeGen/ARM/div.ll

 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV -check-prefix=CHECK-SWDIV-64
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=swift        | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV -check-prefix=CHECK-SWDIV-64 -check-prefix=CHECK-HWDIV-T2
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV -check-prefix=CHECK-SWDIV-64
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r4f   | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-SWDIV -check-prefix=CHECK-SWDIV-64
 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-r5    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV -check-prefix=CHECK-SWDIV-64 -check-prefix=CHECK-HWDIV-T2
 ; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-a8    | \
-; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-EABI -check-prefix=CHECK-EABI-64
+; RUN: llc < %s -mtriple=arm-none-eabi -mcpu=cortex-m23 -march=thumb | \
+; RUN:     FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-HWDIV -check-prefix=CHECK-EABI-64 -check-prefix=CHECK-HWDIV-T1
 
 define i32 @f1(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f1
 ; CHECK-SWDIV: __divsi3
 
 ; CHECK-HWDIV: sdiv
 

 }
 
 define i32 @f3(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f3
 ; CHECK-SWDIV: __modsi3
 
 ; CHECK-HWDIV: sdiv
-; CHECK-HWDIV: mls
+; CHECK-HWDIV-T2-NEXT: mls
+; CHECK-HWDIV-T1-NEXT: muls
+; CHECK-HWDIV-T1-NEXT: subs
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_idivmod
 ; CHECK-EABI-NEXT: mov r0, r1
         %tmp1 = srem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 
 define i32 @f4(i32 %a, i32 %b) {
 entry:
 ; CHECK-LABEL: f4
 ; CHECK-SWDIV: __umodsi3
 
 ; CHECK-HWDIV: udiv
-; CHECK-HWDIV: mls
+; CHECK-HWDIV-T2-NEXT: mls
+; CHECK-HWDIV-T1-NEXT: muls
+; CHECK-HWDIV-T1-NEXT: subs
 
 ; EABI MODE = Remainder in R1, quotient in R0
 ; CHECK-EABI: __aeabi_uidivmod
 ; CHECK-EABI-NEXT: mov r0, r1
         %tmp1 = urem i32 %a, %b         ; <i32> [#uses=1]
         ret i32 %tmp1
 }
 
 
 define i64 @f5(i64 %a, i64 %b) {
 entry:
 ; CHECK-LABEL: f5
-; CHECK-SWDIV: __moddi3
-
-; CHECK-HWDIV: __moddi3
+; CHECK-SWDIV-64: __moddi3
 
 ; EABI MODE = Remainder in R2-R3, quotient in R0-R1
-; CHECK-EABI: __aeabi_ldivmod
-; CHECK-EABI-NEXT: mov r0, r2
-; CHECK-EABI-NEXT: mov r1, r3
+; CHECK-EABI-64: __aeabi_ldivmod
+; CHECK-EABI-64-NEXT: mov r0, r2
+; CHECK-EABI-64-NEXT: mov r1, r3
         %tmp1 = srem i64 %a, %b         ; <i64> [#uses=1]
         ret i64 %tmp1
 }
 
 define i64 @f6(i64 %a, i64 %b) {
 entry:
 ; CHECK-LABEL: f6
-; CHECK-SWDIV: __umoddi3
-
-; CHECK-HWDIV: __umoddi3
+; CHECK-SWDIV-64: __umoddi3
 
 ; EABI MODE = Remainder in R2-R3, quotient in R0-R1
-; CHECK-EABI: __aeabi_uldivmod
-; CHECK-EABI-NEXT: mov r0, r2
-; CHECK-EABI-NEXT: mov r1, r3
+; CHECK-EABI-64: __aeabi_uldivmod
+; CHECK-EABI-64-NEXT: mov r0, r2
+; CHECK-EABI-64-NEXT: mov r1, r3
         %tmp1 = urem i64 %a, %b         ; <i64> [#uses=1]
         ret i64 %tmp1
 }

test/CodeGen/ARM/movt.ll

 ; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 ; rdar://7317664
 
 ; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8m.base -mcpu=cortex-m23 %s -o - | FileCheck %s --check-prefix=NOMOVT
 
 define i32 @t(i32 %X) nounwind {
 ; CHECK-LABEL: t:
 ; CHECK: movt r{{[0-9]}}, #65535
+; NOMOVT-LABEL: t:
+; NOMOVT-NOT: movt r{{[0-9]}}, #65535
+; NOMOVT: ldr r{{[0-9]}}, .LCP
 entry:
   %0 = or i32 %X, -65536
   ret i32 %0
 }
 
 define i32 @t2(i32 %X) nounwind {
 ; CHECK-LABEL: t2:
 ; CHECK: movt r{{[0-9]}}, #65534
+; NOMOVT-LABEL: t2:
+; NOMOVT-NOT: movt r{{[0-9]}}, #65534
+; NOMOVT: ldr r{{[0-9]}}, .LCP
 entry:
   %0 = or i32 %X, -131072
   %1 = and i32 %0, -65537
   ret i32 %1
 }

unittests/Support/TargetParserTest.cpp

EXPECT_TRUE(testARMCPU("exynos-m2", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                          ARM::AEK_HWDIV | ARM::AEK_DSP,
                          "8-A"));
   EXPECT_TRUE(testARMCPU("exynos-m3", "armv8-a", "crypto-neon-fp-armv8",
                          ARM::AEK_CRC | ARM::AEK_SEC | ARM::AEK_MP |
                          ARM::AEK_VIRT | ARM::AEK_HWDIVARM |
                          ARM::AEK_HWDIV | ARM::AEK_DSP,
                          "8-A"));
+  EXPECT_TRUE(testARMCPU("cortex-m23", "armv8-m.base", "none",
+                         ARM::AEK_HWDIV, "8-M.Baseline"));
+  EXPECT_TRUE(testARMCPU("cortex-m33", "armv8-m.main", "fpv5-sp-d16",
+                         ARM::AEK_HWDIV | ARM::AEK_DSP, "8-M.Mainline"));
   EXPECT_TRUE(testARMCPU("iwmmxt", "iwmmxt", "none",
                          ARM::AEK_NONE, "iwmmxt"));
   EXPECT_TRUE(testARMCPU("xscale", "xscale", "none",
                          ARM::AEK_NONE, "xscale"));
   EXPECT_TRUE(testARMCPU("swift", "armv7s", "neon-vfpv4",
                          ARM::AEK_HWDIVARM | ARM::AEK_HWDIV | ARM::AEK_DSP,
                          "7-S"));
 }