An assert occurs due to calling getInstructionIndex with a DBG_VALUE instruction because the DBG_VALUE instruction does not have a Slot Index. This occurs in updateRegDefUses.
I'm not sure if this is the correct fix, but there are other places where the call to getInstructionIndex is guarded by a check for DBG_VALUE.
I don't have a reproducible test case because the code that causes the crash is not in-tree. Also, I haven't had any luck reproducing the crash with in-tree code. I tried to generate a test case for ARM because it has composed SubRegs, but I was unsuccessful.
The error occurs, on Hexagon, when introducing a new register class that represents 4 vector registers. The MIR prior to joining the intervals looks like the code below. In the example, the wsub_lo SubReg contains a vsub_hi and vsub_lo register.
%vreg2<def> = load DBG_VALUE %vreg2, %noreg, !"a", %vreg4:vsub_lo<def,read-undef> = COPY %vreg2 %vreg6:wsub_lo<def,read-undef> = COPY %vreg4 %vreg6:wsub_hi<def> = COPY %vreg4
After %vreg2 and %vreg4:vsub_lo are coalesced:
%vreg4:vsub_lo<def,read-undef> = load DBG_VALUE %vreg4:vsub_lo<undef>, %noreg, !"a", %vreg6:wsub_lo<def,read-undef> = COPY %vreg4 %vreg6:wsub_hi<def> = COPY %vreg4
The DBG_VALUE that has a sub register results in the call to getInstructionIndex and the assert.