[XRay][Arm32] Reduce the portion of the stub and implement more staging for tail calls - in LLVM

[rSerge]

Summary

This patch provides more staging for tail calls in XRay Arm32 . When the logging part of XRay is ready for tail calls, its support in the core part of XRay Arm32 may be as easy as changing the number passed to the handler from 1 to 2.
Coupled patch:

• https://reviews.llvm.org/D28674

[rSerge]

Removed the changes fixing Arm32 XRay (as they are in a separate patch https://reviews.llvm.org/D28624 ).

[rengolin]

Where is this used?

[rSerge]

In D28673#645485, @rengolin wrote:

Where is this used?

This virtual function is called via a pointer to a base class in XRayInstrumentation.cpp : see the body of void XRayInstrumentation::prependRetWithPatchableExit(MachineFunction &MF, const TargetInstrInfo *TII).

[rSerge]

Ping?

[dberris]

LGTM

[rSerge]

Reached mainline in revision 293185.

lib/Target/ARM/ARMAsmPrinter.cpp

if (Subtarget->isTargetCOFF()) {
     OutStreamer->EmitCOFFSymbolStorageClass(Scl);
     OutStreamer->EmitCOFFSymbolType(Type);
     OutStreamer->EndCOFFSymbolDef();
   }
 
   // Emit the rest of the function body.
   EmitFunctionBody();
 
+  // Emit the XRay table for this function.
+  emitXRayTable();
+
   // If we need V4T thumb mode Register Indirect Jump pads, emit them.
   // These are created per function, rather than per TU, since it's
   // relatively easy to exceed the thumb branch range within a TU.
   if (! ThumbIndirectPads.empty()) {
     OutStreamer->EmitAssemblerFlag(MCAF_Code16);
     EmitAlignment(1);
     for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
       OutStreamer->EmitLabel(ThumbIndirectPads[i].second);

lib/Target/ARM/ARMBaseInstrInfo.h

 public:
   // Return whether the target has an explicit NOP encoding.
   bool hasNOP() const;
 
   virtual void getNoopForElfTarget(MCInst &NopInst) const {
     getNoopForMachoTarget(NopInst);
   }
 
+  bool isTailCall(const MachineInstr &Inst) const override;
+
   // Return the non-pre/post incrementing version of 'Opc'. Return 0
   // if there is not such an opcode.
   virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
 
   MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
                                       MachineInstr &MI,
                                       LiveVariables *LV) const override;
 

lib/Target/ARM/ARMBaseInstrInfo.cpp

AddDefaultPred(
           .addImm(96));
   MI.addRegisterKilled(DReg, TRI, true);
 }
 
 bool ARMBaseInstrInfo::hasNOP() const {
   return Subtarget.getFeatureBits()[ARM::HasV6KOps];
 }
 
+bool ARMBaseInstrInfo::isTailCall(const MachineInstr &Inst) const
+{
+  switch (Inst.getOpcode()) {
+  case ARM::TAILJMPd:
+  case ARM::TAILJMPr:
+  case ARM::TCRETURNdi:
+  case ARM::TCRETURNri:
+    return true;
+  default:
+    return false;
+  }
+}
+
 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
   if (MI->getNumOperands() < 4)
     return true;
   unsigned ShOpVal = MI->getOperand(3).getImm();
   unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
   // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
   if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
       ((ShImm == 1 || ShImm == 2) &&