[ARM] CodeGen: Remove AddDefaultCC

[rovka]

Summary

Replace all uses of AddDefaultCC with add(condCodeOp()).
The transformation has been done automatically with a custom tool based on Clang
AST Matchers + RefactoringTool.

[MatzeB]

LGTM

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h

 /// predicate register is assumed to be 0 (no register), but you can pass in a
 /// \p PredReg if that is not the case.
 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
                                                     unsigned PredReg = 0) {
   return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
            MachineOperand::CreateReg(PredReg, 0)}};
 }
 
-// FIXME: Replace with something that returns a MachineOperand
-static inline
-const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
-  return MIB.addReg(0);
+/// Get the operand corresponding to the conditional code result. By default,
+/// this is 0 (no register).
+static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
+  return MachineOperand::CreateReg(CCReg, 0);
 }
 
-// FIXME: Replace with something that returns a MachineOperand
+// FIXME: Replace with something that returns a MachineOperand directly.
 static inline
 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
                                           bool isDead = false) {
   return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
 }
 
 // FIXME: Replace with something that returns a MachineOperand
 static inline

llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator I,
                                    const DebugLoc &DL, unsigned DestReg,
                                    unsigned SrcReg, bool KillSrc) const {
   bool GPRDest = ARM::GPRRegClass.contains(DestReg);
   bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
 
   if (GPRDest && GPRSrc) {
-    AddDefaultCC(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
-                     .addReg(SrcReg, getKillRegState(KillSrc))
-                     .add(predOps(ARMCC::AL)));
+    BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
+        .add(predOps(ARMCC::AL))
+        .add(condCodeOp());
     return;
   }
 
   bool SPRDest = ARM::SPRRegClass.contains(DestReg);
   bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
 
   unsigned Opc = 0;
   if (SPRDest && SPRSrc)

 #endif
     Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
     // VORR takes two source operands.
     if (Opc == ARM::VORRq)
       Mov.addReg(Src);
     Mov = Mov.add(predOps(ARMCC::AL));
     // MOVr can set CC.
     if (Opc == ARM::MOVr)
-      Mov = AddDefaultCC(Mov);
+      Mov = Mov.add(condCodeOp());
   }
   // Add implicit super-register defs and kills to the last instruction.
   Mov->addRegisterDefined(DestReg, TRI);
   if (KillSrc)
     Mov->addRegisterKilled(SrcReg, TRI);
 }
 
 const MachineInstrBuilder &
ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
   if (Invert)
     NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
   else
     NewMI.addImm(CondCode);
   NewMI.add(MI.getOperand(4));
 
   // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
   if (NewMI->hasOptionalDef())
-    AddDefaultCC(NewMI);
+    NewMI.add(condCodeOp());
 
   // The output register value when the predicate is false is an implicit
   // register operand tied to the first def.
   // The tie makes the register allocator ensure the FalseReg is allocated the
   // same register as operand 0.
   FalseReg.setImplicit();
   NewMI.add(FalseReg);
   NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
case ARM::t2EORrr: {
     }
   }
   }
 
   unsigned OpIdx = Commute ? 2 : 1;
   unsigned Reg1 = UseMI.getOperand(OpIdx).getReg();
   bool isKill = UseMI.getOperand(OpIdx).isKill();
   unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
-  AddDefaultCC(BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
-                       get(NewUseOpc), NewReg)
-                   .addReg(Reg1, getKillRegState(isKill))
-                   .addImm(SOImmValV1)
-                   .add(predOps(ARMCC::AL)));
+  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
+          NewReg)
+      .add(predOps(ARMCC::AL))
+      .add(condCodeOp());
   UseMI.setDesc(get(NewUseOpc));
   UseMI.getOperand(1).setReg(NewReg);
   UseMI.getOperand(1).setIsKill();
   UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
   DefMI.eraseFromParent();
   return true;
 }
 

llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp

materializeFrameBaseRegister(MachineBasicBlock *MBB,
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   const MCInstrDesc &MCID = TII.get(ADDriOpc);
   MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
 
   MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
     .addFrameIndex(FrameIdx).addImm(Offset);
 
   if (!AFI->isThumb1OnlyFunction())
-    AddDefaultCC(MIB.add(predOps(ARMCC::AL)));
+    MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
 }
 
 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
                                             int64_t Offset) const {
   MachineBasicBlock &MBB = *MI.getParent();
   MachineFunction &MF = *MBB.getParent();
   const ARMBaseInstrInfo &TII =
       *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());

llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

case ARM::Int_eh_sjlj_dispatchsetup: {
           unsigned MaxAlign = MFI.getMaxAlignment();
           assert (!AFI->isThumb1OnlyFunction());
           // Emit bic r6, r6, MaxAlign
           assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
                                     "immediates larger than 256 with all lower "
                                     "bits set.");
           unsigned bicOpc = AFI->isThumbFunction() ?
             ARM::t2BICri : ARM::BICri;
-          AddDefaultCC(
-              BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
-                  .addReg(ARM::R6, RegState::Kill)
-                  .addImm(MaxAlign - 1)
-                  .add(predOps(ARMCC::AL)));
+              .add(predOps(ARMCC::AL))
+              .add(condCodeOp());
         }
 
       }
       MI.eraseFromParent();
       return true;
     }
 
     case ARM::MOVsrl_flag:

llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
 
   // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
   // defines CPSR. All other OptionalDefines in ARM are the CCR register.
   bool CPSR = false;
   if (DefinesOptionalPredicate(MI, &CPSR)) {
     if (CPSR)
       AddDefaultT1CC(MIB);
     else
-      AddDefaultCC(MIB);
+      MIB.add(condCodeOp());
   }
   return MIB;
 }
 
 unsigned ARMFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
                                      const TargetRegisterClass *RC,
                                      unsigned Op0, bool Op0IsKill) {
   unsigned ResultReg = createResultReg(RC);
MachineInstrBuilder MIB = BuildMI(
         *FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opcode), ResultReg);
     if (setsCPSR)
       MIB.addReg(ARM::CPSR, RegState::Define);
     SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
     MIB.addReg(SrcReg, isKill * RegState::Kill)
         .addImm(ImmEnc)
         .add(predOps(ARMCC::AL));
     if (hasS)
-      AddDefaultCC(MIB);
+      MIB.add(condCodeOp());
     // Second instruction consumes the first's result.
     SrcReg = ResultReg;
   }
 
   return ResultReg;
 }
 
 bool ARMFastISel::SelectIntExt(const Instruction *I) {

llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp

if (!AFI->isThumbFunction()) {
     //   lsr Reg, Reg, log2(Alignment)
     //   lsl Reg, Reg, log2(Alignment)
     if (CanUseBFC) {
       BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
           .addReg(Reg, RegState::Kill)
           .addImm(~AlignMask)
           .add(predOps(ARMCC::AL));
     } else if (AlignMask <= 255) {
-      AddDefaultCC(BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
-                       .addReg(Reg, RegState::Kill)
-                       .addImm(AlignMask)
-                       .add(predOps(ARMCC::AL)));
+      BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
+          .add(predOps(ARMCC::AL))
+          .add(condCodeOp());
     } else {
       assert(!MustBeSingleInstruction &&
              "Shouldn't call emitAligningInstructions demanding a single "
              "instruction to be emitted for large stack alignment for a target "
              "without BFC.");
-      AddDefaultCC(BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
-                       .addReg(Reg, RegState::Kill)
-                       .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero))
-                       .add(predOps(ARMCC::AL)));
-      AddDefaultCC(BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
-                       .addReg(Reg, RegState::Kill)
-                       .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero))
-                       .add(predOps(ARMCC::AL)));
+      BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
+          .add(predOps(ARMCC::AL))
+          .add(condCodeOp());
+      BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
+          .add(predOps(ARMCC::AL))
+          .add(condCodeOp());
     }
   } else {
     // Since this is only reached for Thumb-2 targets, the BFC instruction
     // should always be available.
     assert(CanUseBFC);
     BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
         .addReg(Reg, RegState::Kill)
         .addImm(~AlignMask)
case CodeModel::JITDefault:
       BuildMI(MBB, MBBI, dl, TII.get(ARM::tBLXr))
         .addImm((unsigned)ARMCC::AL).addReg(0)
         .addReg(ARM::R12, RegState::Kill)
         .addReg(ARM::R4, RegState::Implicit)
         .setMIFlags(MachineInstr::FrameSetup);
       break;
     }
 
-    AddDefaultCC(BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
-                     .addReg(ARM::SP, RegState::Kill)
-                     .addReg(ARM::R4, RegState::Kill)
-                     .setMIFlags(MachineInstr::FrameSetup)
-                     .add(predOps(ARMCC::AL)));
+    BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
+        .add(predOps(ARMCC::AL))
+        .add(condCodeOp());
     NumBytes = 0;
   }
 
   if (NumBytes) {
     // Adjust SP after all the callee-save spills.
     if (AFI->getNumAlignedDPRCS2Regs() == 0 &&
         tryFoldSPUpdateIntoPushPop(STI, MF, &*LastPush, NumBytes))
       DefCFAOffsetCandidates.addExtraBytes(LastPush, NumBytes);
static void emitAlignedDPRCS2Spills(MachineBasicBlock &MBB,
   //
   bool isThumb = AFI->isThumbFunction();
   assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
   AFI->setShouldRestoreSPFromFP(true);
 
   // sub r4, sp, #numregs * 8
   // The immediate is <= 64, so it doesn't need any special encoding.
   unsigned Opc = isThumb ? ARM::t2SUBri : ARM::SUBri;
-  AddDefaultCC(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
-                   .addReg(ARM::SP)
-                   .addImm(8 * NumAlignedDPRCS2Regs)
-                   .add(predOps(ARMCC::AL)));
+  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
+      .add(predOps(ARMCC::AL))
+      .add(condCodeOp());
 
   unsigned MaxAlign = MF.getFrameInfo().getMaxAlignment();
   // We must set parameter MustBeSingleInstruction to true, since
   // skipAlignedDPRCS2Spills expects exactly 3 instructions to perform
   // stack alignment.  Luckily, this can always be done since all ARM
   // architecture versions that support Neon also support the BFC
   // instruction.
   emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
 
   // mov sp, r4
   // The stack pointer must be adjusted before spilling anything, otherwise
   // the stack slots could be clobbered by an interrupt handler.
   // Leave r4 live, it is used below.
   Opc = isThumb ? ARM::tMOVr : ARM::MOVr;
   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
                                 .addReg(ARM::R4)
                                 .add(predOps(ARMCC::AL));
   if (!isThumb)
-    AddDefaultCC(MIB);
+    MIB.add(condCodeOp());
 
   // Now spill NumAlignedDPRCS2Regs registers starting from d8.
   // r4 holds the stack slot address.
   unsigned NextReg = ARM::D8;
 
   // 16-byte aligned vst1.64 with 4 d-regs and address writeback.
   // The writeback is only needed when emitting two vst1.64 instructions.
   if (NumAlignedDPRCS2Regs >= 6) {
static void emitAlignedDPRCS2Restores(MachineBasicBlock &MBB,
   // This can be fairly complicated if the stack frame is large, so just use
   // the normal frame index elimination mechanism to do it.  This code runs as
   // the initial part of the epilog where the stack and base pointers haven't
   // been changed yet.
   bool isThumb = AFI->isThumbFunction();
   assert(!AFI->isThumb1OnlyFunction() && "Can't realign stack for thumb1");
 
   unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
-  AddDefaultCC(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
-                   .addFrameIndex(D8SpillFI)
-                   .addImm(0)
-                   .add(predOps(ARMCC::AL)));
+  BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
+      .add(predOps(ARMCC::AL))
+      .add(condCodeOp());
 
   // Now restore NumAlignedDPRCS2Regs registers starting from d8.
   unsigned NextReg = ARM::D8;
 
   // 16-byte aligned vld1.64 with 4 d-regs and writeback.
   if (NumAlignedDPRCS2Regs >= 6) {
     unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
                                                &ARM::QQPRRegClass);
if (Thumb) {
     BuildMI(McrMBB, DL, TII.get(ARM::MOVr), ScratchReg1)
         .addReg(ARM::SP)
         .add(predOps(ARMCC::AL))
         .addReg(0);
   }
 
   // sub SR1, sp, #StackSize
   if (!CompareStackPointer && Thumb) {
-    AddDefaultCC(BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1))
+    BuildMI(McrMBB, DL, TII.get(ARM::tSUBi8), ScratchReg1)
+        .add(condCodeOp())
         .addReg(ScratchReg1)
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL));
   } else if (!CompareStackPointer) {
     BuildMI(McrMBB, DL, TII.get(ARM::SUBri), ScratchReg1)
         .addReg(ARM::SP)
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL))
void ARMFrameLowering::adjustForSegmentedStacks(
 
   // Calling __morestack(StackSize, Size of stack arguments).
   // __morestack knows that the stack size requested is in SR0(r4)
   // and amount size of stack arguments is in SR1(r5).
 
   // Pass first argument for the __morestack by Scratch Register #0.
   //   The amount size of stack required
   if (Thumb) {
-    AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0))
+    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg0)
+        .add(condCodeOp())
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL));
   } else {
     BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg0)
         .addImm(AlignedStackSize)
         .add(predOps(ARMCC::AL))
         .addReg(0);
   }
   // Pass second argument for the __morestack by Scratch Register #1.
   //   The amount size of stack consumed to save function arguments.
   if (Thumb) {
-    AddDefaultCC(BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1))
+    BuildMI(AllocMBB, DL, TII.get(ARM::tMOVi8), ScratchReg1)
+        .add(condCodeOp())
         .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
         .add(predOps(ARMCC::AL));
   } else {
     BuildMI(AllocMBB, DL, TII.get(ARM::MOVi), ScratchReg1)
         .addImm(alignToARMConstant(ARMFI->getArgumentStackSize()))
         .add(predOps(ARMCC::AL))
         .addReg(0);
   }

llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

if (isThumb2) {
     //   str    r5, [$jbuf, #+4] ; &jbuf[1]
     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
     BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
         .addConstantPoolIndex(CPI)
         .addMemOperand(CPMMO)
         .add(predOps(ARMCC::AL));
     // Set the low bit because of thumb mode.
     unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
-    AddDefaultCC(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
-                     .addReg(NewVReg1, RegState::Kill)
-                     .addImm(0x01)
-                     .add(predOps(ARMCC::AL)));
+    BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
+        .add(predOps(ARMCC::AL))
+        .add(condCodeOp());
     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
     BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
       .addReg(NewVReg2, RegState::Kill)
       .addImm(PCLabelId);
     BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
         .addReg(NewVReg3, RegState::Kill)
         .addFrameIndex(FI)
         .addImm(36) // &jbuf[1] :: pc
BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
       .addReg(ARM::CPSR);
 
     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
     BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT), NewVReg3)
         .addJumpTableIndex(MJTI)
         .add(predOps(ARMCC::AL));
 
     unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
-    AddDefaultCC(BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
-                     .addReg(NewVReg3, RegState::Kill)
-                     .addReg(NewVReg1)
-                     .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
-                     .add(predOps(ARMCC::AL)));
+    BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
+        .add(predOps(ARMCC::AL))
+        .add(condCodeOp());
 
     BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
       .addReg(NewVReg4, RegState::Kill)
       .addReg(NewVReg1)
       .addJumpTableIndex(MJTI);
   } else if (Subtarget->isThumb()) {
     unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
     BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
if (Subtarget->isThumb2()) {
     }
 
     BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
       .addMBB(TrapBB)
       .addImm(ARMCC::HI)
       .addReg(ARM::CPSR);
 
     unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
-    AddDefaultCC(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
-                     .addReg(NewVReg1)
-                     .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))
-                     .add(predOps(ARMCC::AL)));
+    BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
+        .add(predOps(ARMCC::AL))
+        .add(condCodeOp());
     unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
     BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
         .addJumpTableIndex(MJTI)
         .add(predOps(ARMCC::AL));
 
     MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
         MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
     unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
MachineInstrBuilder MIB =
         BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
     MIB = AddDefaultT1CC(MIB);
     MIB.addReg(varPhi).addImm(UnitSize);
     MIB.add(predOps(ARMCC::AL));
   } else {
     MachineInstrBuilder MIB =
         BuildMI(*BB, BB->end(), dl,
                 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
-    AddDefaultCC(MIB.addReg(varPhi).addImm(UnitSize).add(predOps(ARMCC::AL)));
+    MIB.addReg(varPhi)
+        .addImm(UnitSize)
+        .add(predOps(ARMCC::AL))
+        .add(condCodeOp());
     MIB->getOperand(5).setReg(ARM::CPSR);
     MIB->getOperand(5).setIsDef(true);
   }
   BuildMI(*BB, BB->end(), dl,
           TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
       .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
 
   // loopMBB can loop back to loopMBB or fall through to exitMBB.
BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
       .addReg(Reg, RegState::Kill)
       .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
       .addReg(ARM::R4, RegState::Implicit | RegState::Define)
       .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
     break;
   }
   }
 
-  AddDefaultCC(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
-                   .addReg(ARM::SP, RegState::Kill)
-                   .addReg(ARM::R4, RegState::Kill)
-                   .setMIFlags(MachineInstr::FrameSetup)
-                   .add(predOps(ARMCC::AL)));
+  BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
+      .add(predOps(ARMCC::AL))
+      .add(condCodeOp());
 
   MI.eraseFromParent();
   return MBB;
 }
 
 MachineBasicBlock *
 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr &MI,
                                        MachineBasicBlock *MBB) const {

llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp

bool ARMInstructionSelector::select(MachineInstr &I) const {
   }
 
   MachineInstrBuilder MIB{MF, I};
 
   using namespace TargetOpcode;
   switch (I.getOpcode()) {
   case G_ADD:
     I.setDesc(TII.get(ARM::ADDrr));
-    AddDefaultCC(MIB.add(predOps(ARMCC::AL)));
+    MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
     break;
   case G_FRAME_INDEX:
     // Add 0 to the given frame index and hope it will eventually be folded into
     // the user(s).
     I.setDesc(TII.get(ARM::ADDri));
-    AddDefaultCC(MIB.addImm(0).add(predOps(ARMCC::AL)));
+    MIB.addImm(0).add(predOps(ARMCC::AL)).add(condCodeOp());
     break;
   case G_LOAD:
     I.setDesc(TII.get(ARM::LDRi12));
     MIB.addImm(0).add(predOps(ARMCC::AL));
     break;
   default:
     return false;
   }
 
   return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
 }

llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp

while (NumBytes) {
 
     // Build the new ADD / SUB.
     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
                                   .addReg(BaseReg, RegState::Kill)
                                   .addImm(ThisVal)
                                   .add(predOps(ARMCC::AL))
                                   .setMIFlags(MIFlags);
     if (HasCCOut)
-      AddDefaultCC(MIB);
+      MIB.add(condCodeOp());
 
     BaseReg = DestReg;
   }
 }
 
 static unsigned
 negativeOffsetOpcode(unsigned opcode)
 {