[PowerPC] Implement missing instructions.

[jtony]

Summary

Implement the following missing instructions from ISA 2.06:
fctidu[.], fctiwu[.], ftdiv, ftsqrt

[hfinkel]

lib/Target/PowerPC/PPCISelLowering.cpp

1035 ↗

(On Diff #83077)

The spacing is off here (but unless you're adding code that uses these, save this for later).

lib/Target/PowerPC/PPCISelLowering.h

51

Please add these only in a patch that uses them.

[jtony]

Address the comments from Hal.

[nemanjai]

I don't think that addressing the one inline comment requires another review - please address it, test it and then commit.

LGTM

lib/Target/PowerPC/PPCInstrInfo.td

2175

I don't think this is necessary on this def or the next.

lib/Target/PowerPC/PPCISelLowering.h

enum NodeType : unsigned {
       FCFIDU, FCFIDS, FCFIDUS,
 
       /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
       /// operand, producing an f64 value containing the integer representation
       /// of that FP value.
       FCTIDZ, FCTIWZ,
 
       /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
-      /// unsigned integers.
+      /// unsigned integers with round toward Zero.
       FCTIDUZ, FCTIWUZ,
 
       /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
       /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
       VEXTS,
 
       /// Reciprocal estimate instructions (unary FP ops).
       FRE, FRSQRTE,
 

lib/Target/PowerPC/PPCInstr64Bit.td

 let PPC970_Unit = 3, hasSideEffects = 0,
     Uses = [RM] in {  // FPU Operations.
 defm FCFID  : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
                         "fcfid", "$frD, $frB", IIC_FPGeneral,
                         [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
 defm FCTID  : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
                         "fctid", "$frD, $frB", IIC_FPGeneral,
                         []>, isPPC64;
+defm FCTIDU : XForm_26r<63, 942, (outs f8rc:$frD), (ins f8rc:$frB),
+                        "fctidu", "$frD, $frB", IIC_FPGeneral,
+                        []>, isPPC64;
 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
                         "fctidz", "$frD, $frB", IIC_FPGeneral,
                         [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
 
 defm FCFIDU  : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
                         "fcfidu", "$frD, $frB", IIC_FPGeneral,
                         [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
 defm FCFIDS  : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),

lib/Target/PowerPC/PPCInstrFormats.td

class XForm_17<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   let Inst{6-8}   = BF;
   let Inst{9-10}  = 0;
   let Inst{11-15} = FRA;
   let Inst{16-20} = FRB;
   let Inst{21-30} = xo;
   let Inst{31}    = 0;
 }
 
+class XForm_17a<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+               InstrItinClass itin>
+  : XForm_17<opcode, xo, OOL, IOL, asmstr, itin > {
+  let FRA = 0;
+}
+
 // Used for QPX
 class XForm_18<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
          : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> FRT;
   bits<5> FRA;
   bits<5> FRB;
 

lib/Target/PowerPC/PPCInstrInfo.td

 let isCompare = 1, hasSideEffects = 0 in {
   def FCMPUS : XForm_17<63, 0, (outs crrc:$crD), (ins f4rc:$fA, f4rc:$fB),
                         "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
   let Interpretation64Bit = 1, isCodeGenOnly = 1 in
   def FCMPUD : XForm_17<63, 0, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
                         "fcmpu $crD, $fA, $fB", IIC_FPCompare>;
 }
 
+let Interpretation64Bit = 1 in {
+def FTDIV: XForm_17<63, 128, (outs crrc:$crD), (ins f8rc:$fA, f8rc:$fB),
+                      "ftdiv $crD, $fA, $fB", IIC_FPCompare>;
+}
+
+let Interpretation64Bit = 1 in {
+def FTSQRT: XForm_17a<63, 160, (outs crrc:$crD), (ins f8rc:$fB),
+                      "ftsqrt $crD, $fB", IIC_FPCompare>;
+}
+
 let Uses = [RM] in {
   let hasSideEffects = 0 in {
   defm FCTIW  : XForm_26r<63, 14, (outs f8rc:$frD), (ins f8rc:$frB),
                           "fctiw", "$frD, $frB", IIC_FPGeneral,
                           []>;
+  defm FCTIWU  : XForm_26r<63, 142, (outs f8rc:$frD), (ins f8rc:$frB),
+                          "fctiwu", "$frD, $frB", IIC_FPGeneral,
+                          []>;
   defm FCTIWZ : XForm_26r<63, 15, (outs f8rc:$frD), (ins f8rc:$frB),
                           "fctiwz", "$frD, $frB", IIC_FPGeneral,
                           [(set f64:$frD, (PPCfctiwz f64:$frB))]>;
 
   defm FRSP   : XForm_26r<63, 12, (outs f4rc:$frD), (ins f8rc:$frB),
                           "frsp", "$frD, $frB", IIC_FPGeneral,
                           [(set f32:$frD, (fpround f64:$frB))]>;
 

test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt

 0xfc 0x40 0x18 0x19
 
 # CHECK: fctid 2, 3                      
 0xfc 0x40 0x1e 0x5c
 
 # CHECK: fctid. 2, 3                     
 0xfc 0x40 0x1e 0x5d
 
+# CHECK: fctidu 2, 3
+0xfc 0x40 0x1f 0x5c
+
+# CHECK: fctidu. 2, 3
+0xfc 0x40 0x1f 0x5d
+
 # CHECK: fctidz 2, 3                     
 0xfc 0x40 0x1e 0x5e
 
 # CHECK: fctidz. 2, 3                    
 0xfc 0x40 0x1e 0x5f
 
 # CHECK: fctiduz 2, 3                    
 0xfc 0x40 0x1f 0x5e
 
 # CHECK: fctiduz. 2, 3                   
 0xfc 0x40 0x1f 0x5f
 
 # CHECK: fctiw 2, 3                      
 0xfc 0x40 0x18 0x1c
 
 # CHECK: fctiw. 2, 3                     
 0xfc 0x40 0x18 0x1d
 
+# CHECK: fctiwu 2, 3
+0xfc 0x40 0x19 0x1c
+
+# CHECK: fctiwu. 2, 3
+0xfc 0x40 0x19 0x1d
+
 # CHECK: fctiwz 2, 3                     
 0xfc 0x40 0x18 0x1e
 
 # CHECK: fctiwz. 2, 3                    
 0xfc 0x40 0x18 0x1f
 
 # CHECK: fctiwuz 2, 3                    
 0xfc 0x40 0x19 0x1e

 0xfc 0x40 0x1b 0x51
 
 # CHECK: frim 2, 3                       
 0xfc 0x40 0x1b 0xd0
 
 # CHECK: frim. 2, 3                      
 0xfc 0x40 0x1b 0xd1
 
+# CHECK: ftdiv 2, 3, 4
+0xfd 0x03 0x21 0x00
+
+#CHECK: ftsqrt 2, 3
+0xfd,0x00,0x19,0x40
+
 # CHECK: fcmpu 2, 3, 4                   
 0xfd 0x03 0x20 0x00
 
 # CHECK: fsel 2, 3, 4, 5                 
 0xfc 0x43 0x29 0x2e
 
 # CHECK: fsel. 2, 3, 4, 5                
 0xfc 0x43 0x29 0x2f

test/MC/PowerPC/ppc64-encoding-fp.s

 # CHECK-LE: frsqrte. 2, 3                   # encoding: [0x35,0x18,0x40,0xfc]
             frsqrte. 2, 3
 # CHECK-BE: frsqrtes 2, 3                   # encoding: [0xec,0x40,0x18,0x34]
 # CHECK-LE: frsqrtes 2, 3                   # encoding: [0x34,0x18,0x40,0xec]
             frsqrtes 2, 3
 # CHECK-BE: frsqrtes. 2, 3                  # encoding: [0xec,0x40,0x18,0x35]
 # CHECK-LE: frsqrtes. 2, 3                  # encoding: [0x35,0x18,0x40,0xec]
             frsqrtes. 2, 3
-# FIXME:    ftdiv 2, 3, 4
-# FIXME:    ftsqrt 2, 3, 4
+
+# CHECK-BE: ftdiv 2, 3, 4                   # encoding: [0xfd,0x03,0x21,0x00]
+# CHECK-LE: ftdiv 2, 3, 4                   # encoding: [0x00,0x21,0x03,0xfd]
+            ftdiv 2, 3, 4
+
+# CHECK-BE: ftsqrt 2, 3                    # encoding: [0xfd,0x00,0x19,0x40]
+# CHECK-LE: ftsqrt 2, 3                    # encoding: [0x40,0x19,0x00,0xfd]
+            ftsqrt 2, 3
 
 # CHECK-BE: fmadd 2, 3, 4, 5                # encoding: [0xfc,0x43,0x29,0x3a]
 # CHECK-LE: fmadd 2, 3, 4, 5                # encoding: [0x3a,0x29,0x43,0xfc]
             fmadd 2, 3, 4, 5
 # CHECK-BE: fmadd. 2, 3, 4, 5               # encoding: [0xfc,0x43,0x29,0x3b]
 # CHECK-LE: fmadd. 2, 3, 4, 5               # encoding: [0x3b,0x29,0x43,0xfc]
             fmadd. 2, 3, 4, 5
 # CHECK-BE: fmadds 2, 3, 4, 5               # encoding: [0xec,0x43,0x29,0x3a]
# CHECK-LE: frsp. 2, 3                      # encoding: [0x19,0x18,0x40,0xfc]
             frsp. 2, 3
 
 # CHECK-BE: fctid 2, 3                      # encoding: [0xfc,0x40,0x1e,0x5c]
 # CHECK-LE: fctid 2, 3                      # encoding: [0x5c,0x1e,0x40,0xfc]
             fctid 2, 3
 # CHECK-BE: fctid. 2, 3                     # encoding: [0xfc,0x40,0x1e,0x5d]
 # CHECK-LE: fctid. 2, 3                     # encoding: [0x5d,0x1e,0x40,0xfc]
             fctid. 2, 3
+
+# CHECK-BE: fctidu 2, 3                      # encoding: [0xfc,0x40,0x1f,0x5c]
+# CHECK-LE: fctidu 2, 3                      # encoding: [0x5c,0x1f,0x40,0xfc]
+            fctidu 2, 3
+# CHECK-BE: fctidu. 2, 3                     # encoding: [0xfc,0x40,0x1f,0x5d]
+# CHECK-LE: fctidu. 2, 3                     # encoding: [0x5d,0x1f,0x40,0xfc]
+            fctidu. 2, 3
+
 # CHECK-BE: fctidz 2, 3                     # encoding: [0xfc,0x40,0x1e,0x5e]
 # CHECK-LE: fctidz 2, 3                     # encoding: [0x5e,0x1e,0x40,0xfc]
             fctidz 2, 3
 # CHECK-BE: fctidz. 2, 3                    # encoding: [0xfc,0x40,0x1e,0x5f]
 # CHECK-LE: fctidz. 2, 3                    # encoding: [0x5f,0x1e,0x40,0xfc]
             fctidz. 2, 3
-# FIXME:    fctidu 2, 3
-# FIXME:    fctidu. 2, 3
+
 # CHECK-BE: fctiduz 2, 3                    # encoding: [0xfc,0x40,0x1f,0x5e]
 # CHECK-LE: fctiduz 2, 3                    # encoding: [0x5e,0x1f,0x40,0xfc]
             fctiduz 2, 3
 # CHECK-BE: fctiduz. 2, 3                   # encoding: [0xfc,0x40,0x1f,0x5f]
 # CHECK-LE: fctiduz. 2, 3                   # encoding: [0x5f,0x1f,0x40,0xfc]
             fctiduz. 2, 3
+
 # CHECK-BE: fctiw 2, 3                      # encoding: [0xfc,0x40,0x18,0x1c]
 # CHECK-LE: fctiw 2, 3                      # encoding: [0x1c,0x18,0x40,0xfc]
             fctiw 2, 3
 # CHECK-BE: fctiw. 2, 3                     # encoding: [0xfc,0x40,0x18,0x1d]
 # CHECK-LE: fctiw. 2, 3                     # encoding: [0x1d,0x18,0x40,0xfc]
             fctiw. 2, 3
+
+# CHECK-BE: fctiwu 2, 3                      # encoding: [0xfc,0x40,0x19,0x1c]
+# CHECK-LE: fctiwu 2, 3                      # encoding: [0x1c,0x19,0x40,0xfc]
+            fctiwu 2, 3
+# CHECK-BE: fctiwu. 2, 3                     # encoding: [0xfc,0x40,0x19,0x1d]
+# CHECK-LE: fctiwu. 2, 3                     # encoding: [0x1d,0x19,0x40,0xfc]
+            fctiwu. 2, 3
+
 # CHECK-BE: fctiwz 2, 3                     # encoding: [0xfc,0x40,0x18,0x1e]
 # CHECK-LE: fctiwz 2, 3                     # encoding: [0x1e,0x18,0x40,0xfc]
             fctiwz 2, 3
 # CHECK-BE: fctiwz. 2, 3                    # encoding: [0xfc,0x40,0x18,0x1f]
 # CHECK-LE: fctiwz. 2, 3                    # encoding: [0x1f,0x18,0x40,0xfc]
             fctiwz. 2, 3
-# FIXME:    fctiwu 2, 3
-# FIXME:    fctiwu. 2, 3
 # CHECK-BE: fctiwuz 2, 3                    # encoding: [0xfc,0x40,0x19,0x1e]
 # CHECK-LE: fctiwuz 2, 3                    # encoding: [0x1e,0x19,0x40,0xfc]
             fctiwuz 2, 3
 # CHECK-BE: fctiwuz. 2, 3                   # encoding: [0xfc,0x40,0x19,0x1f]
 # CHECK-LE: fctiwuz. 2, 3                   # encoding: [0x1f,0x19,0x40,0xfc]
             fctiwuz. 2, 3
 # CHECK-BE: fcfid 2, 3                      # encoding: [0xfc,0x40,0x1e,0x9c]
 # CHECK-LE: fcfid 2, 3                      # encoding: [0x9c,0x1e,0x40,0xfc]