[ARM] ARMLoadStoreOpt generates deprecated T1 STM

[zzheng]

Summary

Fix for

if (isThumb1 && isi32Load && ...) {
  if (...)
  else if (opcode == ARM:tSTRi) 
     ... 
}

and add an test case. This would prevent generating stm r1!, {r1, r0} on Thumb1, where value stored for r1 is UNKONWN.

[jmolloy]

LGTM, thanks!

llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

bool SafeToClobberCPSR = !isThumb1 ||
     (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) ==
      MachineBasicBlock::LQR_Dead);
 
   bool Writeback = isThumb1; // Thumb1 LDM/STM have base reg writeback.
 
   // Exception: If the base register is in the input reglist, Thumb1 LDM is
   // non-writeback.
   // It's also not possible to merge an STR of the base register in Thumb1.
-  if (isThumb1 && isi32Load(Opcode) && ContainsReg(Regs, Base)) {
+  if (isThumb1 && ContainsReg(Regs, Base)) {
     assert(Base != ARM::SP && "Thumb1 does not allow SP in register list");
-    if (Opcode == ARM::tLDRi) {
+    if (Opcode == ARM::tLDRi)
       Writeback = false;
-    } else if (Opcode == ARM::tSTRi) {
+    else if (Opcode == ARM::tSTRi)
       return nullptr;
-    }
-  }
 
   ARM_AM::AMSubMode Mode = ARM_AM::ia;
   // VFP and Thumb2 do not support IB or DA modes. Thumb1 only supports IA.
   bool isNotVFP = isi32Load(Opcode) || isi32Store(Opcode);
   bool haveIBAndDA = isNotVFP && !isThumb2 && !isThumb1;
 
   if (Offset == 4 && haveIBAndDA) {
     Mode = ARM_AM::ib;

llvm/trunk/test/CodeGen/Thumb/stm-deprecated.ll

+; RUN: llc -mtriple=thumbv6m-eabi -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv5e-linux-gnueabi -verify-machineinstrs %s -o - | FileCheck %s
+
+%0 = type { %0*, %0*, i32 }
+
+@x1 = external global %0, align 4
+@x2 = external global %0, align 4
+
+; CHECK: str r0, [r1]
+; CHECK-NEXT: str r1, [r1, #4]
+; CHECK-NOT: stm
+
+define void @foo(i32 %unused, %0* %x) {
+  %first = getelementptr inbounds %0, %0* %x, i32 0, i32 0
+  %second = getelementptr inbounds %0, %0* %x, i32 0, i32 1
+  store %0* @x1, %0** %first
+  store %0* %x, %0** %second
+  unreachable
+}