DAG: Fold out out of bounds insert_vector_elt

[arsenm]

Summary

getNode already prevents formation of out of bounds constant
extract_vector_elts. Do the same for insert_vector_elt.

As came up in D26174

[efriedma]

LGTM with the PPC test fixed.

test/CodeGen/PowerPC/vec_add_sub_quadword.ll

34

Please fix to generate vadduqm.

57

Can you fix this test so it still generates a vsubuqm? Just make the subtract take tmpvec as input instead of tmpvec2.

[efriedma]

Oh, wait, actually we should have a test which explicits checks that we fold the insertelement to undef.

[arsenm]

Fix test

[hfinkel]

LGTM

[arsenm]

r288603

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

if (N1C->getZExtValue())
        return N2;             // select true, X, Y -> X
      return N3;             // select false, X, Y -> Y
     }
 
     if (N2 == N3) return N2;   // select C, X, X -> X
     break;
   case ISD::VECTOR_SHUFFLE:
     llvm_unreachable("should use getVectorShuffle constructor!");
+  case ISD::INSERT_VECTOR_ELT: {
+    ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3);
+    // INSERT_VECTOR_ELT into out-of-bounds element is an UNDEF
+    if (N3C && N3C->getZExtValue() >= N1.getValueType().getVectorNumElements())
+      return getUNDEF(VT);
+    break;
+  }
   case ISD::INSERT_SUBVECTOR: {
     SDValue Index = N3;
     if (VT.isSimple() && N1.getValueType().isSimple()
         && N2.getValueType().isSimple()) {
       assert(VT.isVector() && N1.getValueType().isVector() &&
              N2.getValueType().isVector() &&
              "Insert subvector VTs must be a vectors");
       assert(VT == N1.getValueType() &&

test/CodeGen/PowerPC/vec_add_sub_quadword.ll

 ; Check VMX 128-bit integer operations
 ;
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s
 
+define <1 x i128> @out_of_bounds_insertelement(<1 x i128> %x, i128 %val) nounwind {
+       %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 1
+       %result = add <1 x i128> %x, %tmpvec
+       ret <1 x i128> %result
+; CHECK-LABEL: @out_of_bounds_insertelement
+; CHECK: # BB#0:
+; CHECK-NEXT: blr
+}
+
 define <1 x i128> @test_add(<1 x i128> %x, <1 x i128> %y) nounwind {
        %result = add <1 x i128> %x, %y
        ret <1 x i128> %result
 ; CHECK-LABEL: @test_add
 ; CHECK: vadduqm 2, 2, 3
 }
 
 define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind {
        %result = add <1 x i128> %x, <i128 1>
        ret <1 x i128> %result
 ; CHECK-LABEL: @increment_by_one
 ; CHECK: vadduqm 2, 2, 3
 }
 
 define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
        %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
-       %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
-       %result = add <1 x i128> %x, %tmpvec2
+       %result = add <1 x i128> %x, %tmpvec
        ret <1 x i128> %result
 ; CHECK-LABEL: @increment_by_val
 ; CHECK: vadduqm 2, 2, 3
 }
 
 define <1 x i128> @test_sub(<1 x i128> %x, <1 x i128> %y) nounwind {
        %result = sub <1 x i128> %x, %y
        ret <1 x i128> %result
 ; CHECK-LABEL: @test_sub
 ; CHECK: vsubuqm 2, 2, 3
 }
 
 define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind {
        %result = sub <1 x i128> %x, <i128 1>
        ret <1 x i128> %result
 ; CHECK-LABEL: @decrement_by_one
 ; CHECK: vsubuqm 2, 2, 3
 }
 
 define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
        %tmpvec = insertelement <1 x i128> <i128 0>, i128 %val, i32 0
-       %tmpvec2 = insertelement <1 x i128> %tmpvec, i128 %val, i32 1
-       %result = sub <1 x i128> %x, %tmpvec2
+       %result = sub <1 x i128> %x, %tmpvec
        ret <1 x i128> %result
 ; CHECK-LABEL: @decrement_by_val
-; CHECK: vsubuqm   2, 2, 3
+; CHECK: vsubuqm 2, 2, 3
 }
 
-declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, 
-                                              <1 x i128> %y, 
+declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
+                                              <1 x i128> %y,
                                               <1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x, 
+declare <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
                                              <1 x i128> %y) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x, 
-                                              <1 x i128> %y, 
+declare <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
+                                              <1 x i128> %y,
                                               <1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x, 
-                                              <1 x i128> %y, 
+declare <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
+                                              <1 x i128> %y,
                                               <1 x i128> %z) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x, 
+declare <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
                                              <1 x i128> %y) nounwind readnone
-declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x, 
-                                              <1 x i128> %y, 
+declare <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
+                                              <1 x i128> %y,
                                               <1 x i128> %z) nounwind readnone
 
-define <1 x i128> @test_vaddeuqm(<1 x i128> %x, 
-                                <1 x i128> %y, 
+define <1 x i128> @test_vaddeuqm(<1 x i128> %x,
+                               <1 x i128> %y,
                                  <1 x i128> %z) nounwind {
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x,
                                                          <1 x i128> %y,
                                                          <1 x i128> %z)
   ret <1 x i128> %tmp
 ; CHECK-LABEL: @test_vaddeuqm
 ; CHECK: vaddeuqm 2, 2, 3, 4
 }
 
-define <1 x i128> @test_vaddcuq(<1 x i128> %x, 
+define <1 x i128> @test_vaddcuq(<1 x i128> %x,
                                <1 x i128> %y) nounwind {
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddcuq(<1 x i128> %x,
                                                         <1 x i128> %y)
   ret <1 x i128> %tmp
 ; CHECK-LABEL: @test_vaddcuq
 ; CHECK: vaddcuq 2, 2, 3
 }
 
-define <1 x i128> @test_vaddecuq(<1 x i128> %x, 
-                                <1 x i128> %y, 
+define <1 x i128> @test_vaddecuq(<1 x i128> %x,
+                               <1 x i128> %y,
                                  <1 x i128> %z) nounwind {
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vaddecuq(<1 x i128> %x,
                                                          <1 x i128> %y,
                                                          <1 x i128> %z)
   ret <1 x i128> %tmp
 ; CHECK-LABEL: @test_vaddecuq
 ; CHECK: vaddecuq 2, 2, 3, 4
 }
 
-define <1 x i128> @test_vsubeuqm(<1 x i128> %x, 
-                                <1 x i128> %y, 
+define <1 x i128> @test_vsubeuqm(<1 x i128> %x,
+                               <1 x i128> %y,
                                  <1 x i128> %z) nounwind {
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubeuqm(<1 x i128> %x,
                                                          <1 x i128> %y,
                                                          <1 x i128> %z)
   ret <1 x i128> %tmp
 ; CHECK-LABEL: test_vsubeuqm
 ; CHECK: vsubeuqm 2, 2, 3, 4
 }
 
-define <1 x i128> @test_vsubcuq(<1 x i128> %x, 
+define <1 x i128> @test_vsubcuq(<1 x i128> %x,
                                <1 x i128> %y) nounwind {
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubcuq(<1 x i128> %x,
                                                         <1 x i128> %y)
   ret <1 x i128> %tmp
 ; CHECK-LABEL: test_vsubcuq
 ; CHECK: vsubcuq 2, 2, 3
 }
 
-define <1 x i128> @test_vsubecuq(<1 x i128> %x, 
-                                <1 x i128> %y, 
+define <1 x i128> @test_vsubecuq(<1 x i128> %x,
+                               <1 x i128> %y,
                                  <1 x i128> %z) nounwind {
   %tmp = tail call <1 x i128> @llvm.ppc.altivec.vsubecuq(<1 x i128> %x,
                                                          <1 x i128> %y,
                                                          <1 x i128> %z)
   ret <1 x i128> %tmp
 ; CHECK-LABEL: test_vsubecuq
 ; CHECK: vsubecuq 2, 2, 3, 4
 }
 

test/CodeGen/X86/avx512-insert-extract.ll

; SKX-NEXT:    retq
   %r1 = insertelement <4 x i64> %x, i64 %val, i32 1
   %r2 = insertelement <4 x i64> %r1, i64 %y, i32 3
   ret <4 x i64> %r2
 }
 
 define <2 x i64> @insert_v2i64(<2 x i64> %x, i64 %y , i64* %ptr) {
 ; KNL-LABEL: insert_v2i64:
 ; KNL:       ## BB#0:
+; KNL-NEXT:    vpinsrq $0, %rdi, %xmm0, %xmm0
 ; KNL-NEXT:    vpinsrq $1, (%rsi), %xmm0, %xmm0
-; KNL-NEXT:    vpinsrq $3, %rdi, %xmm0, %xmm0
 ; KNL-NEXT:    retq
 ;
 ; SKX-LABEL: insert_v2i64:
 ; SKX:       ## BB#0:
+; SKX-NEXT:    vpinsrq $0, %rdi, %xmm0, %xmm0
 ; SKX-NEXT:    vpinsrq $1, (%rsi), %xmm0, %xmm0
-; SKX-NEXT:    vpinsrq $3, %rdi, %xmm0, %xmm0
 ; SKX-NEXT:    retq
   %val = load i64, i64* %ptr
   %r1 = insertelement <2 x i64> %x, i64 %val, i32 1
-  %r2 = insertelement <2 x i64> %r1, i64 %y, i32 3
+  %r2 = insertelement <2 x i64> %r1, i64 %y, i32 0
   ret <2 x i64> %r2
 }
 
 define <16 x i32> @insert_v16i32(<16 x i32> %x, i32 %y, i32* %ptr) {
 ; KNL-LABEL: insert_v16i32:
 ; KNL:       ## BB#0:
 ; KNL-NEXT:    vpinsrd $1, (%rsi), %xmm0, %xmm1
 ; KNL-NEXT:    vinserti32x4 $0, %xmm1, %zmm0, %zmm0