[SelectionDAG] Do not increment SDNodeOrder for debug intrinsics.

[fhahn]

Summary

Some parts of CodeGen rely on the IR order (e.g. ScheduleDAGRRList)
and debug intrinsics previously affected the ordering.

This problem was found using check_cfc.py. With this patch, the build
failures for llvm's test-suite with check_cfc.py go from 113 down to 77
in x86_64.

[MatzeB]

Adding aprantl for debug info stuff.

[MatzeB]

The description sounds similar to https://reviews.llvm.org/D25318

[aprantl]

Can't say that I fully understand the implication of this (I don't know what the node order is used for), but given your explanation this appears to be fine.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

4975 ↗

(On Diff #79757)

Extra whitespace :-)

[aprantl]

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

873 ↗

(On Diff #79757)

Any way the purpose of this condition could be documented?

[fhahn]

Thanks @MatzeB I wasn't aware of this review! It looks like it addresses a similar problem, but the test case is different. I'll test my change with the test case from the D25318.

[fhahn]

Added a comment and removed stray line.

[fhahn]

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

873 ↗

(On Diff #79757)

I hope my comment change makes is clearer.

[fhahn]

After having a closer look at D25318 I think it solves the problem in a slightly better way.

[fhahn]

Upload 2 test cases for use with D25318

[fhahn]

Abandoned, because merged in rL292485

test/CodeGen/AArch64/selectiondag-order.ll

+; Check that debug intrinsics do not affect code generation.
+
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=AARCH64-CHECK %s
+
+define i64 @simulate(<2 x i32> %a) {
+entry:
+  %rand = tail call i64 @lrand48()
+  br label %body
+
+body:                                        ; preds = %body, %entry
+  %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
+  %add = add <2 x i32> %0, %a
+  %rand1 = tail call i64 @lrand48() #3
+  %cmp = icmp eq i64 %rand1, 0
+  br i1 %cmp, label %end, label %body
+
+end:                                        ; preds = %body
+  %c = bitcast <2 x i32> %add to i64
+  %res = add i64 %rand, %c
+  ret i64 %res
+}
+
+; AARCH64-CHECK: simulate:
+; AARCH64-CHECK: movi d9, #0000000000000000
+; AARCH64-CHECK: bl lrand48
+; AARCH64-CHECK: mov x19, x0
+; AARCH64-CHECK: BB0_1:
+
+
+define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr  {
+entry:
+  %rand = tail call i64 @lrand48() #3
+  tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8
+  br label %body
+
+body:                                        ; preds = %body, %entry
+  %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
+  %add = add <2 x i32> %0, %a
+  %rand1 = tail call i64 @lrand48() #3
+  %cmp = icmp eq i64 %rand1, 0
+  br i1 %cmp, label %end, label %body
+
+end:                                        ; preds = %body
+  %c = bitcast <2 x i32> %add to i64
+  %res = add i64 %rand, %c
+  ret i64 %res
+}
+
+; AARCH64-CHECK: simulateWithDebugIntrinsic
+; AARCH64-CHECK: movi d9, #0000000000000000
+; AARCH64-CHECK: bl lrand48
+; AARCH64-CHECK: mov x19, x0
+; AARCH64-CHECK: BB1_1:
+
+
+define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr  {
+entry:
+  %rand = tail call i64 @lrand48() #3
+  tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8
+  br label %body
+
+body:                                        ; preds = %body, %entry
+  %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
+  %add = add <2 x i32> %0, %a
+  %rand1 = tail call i64 @lrand48() #3
+  %cmp = icmp eq i64 %rand1, 0
+  br i1 %cmp, label %end, label %body
+
+end:                                        ; preds = %body
+  %c = bitcast <2 x i32> %add to i64
+  %res = add i64 %rand, %c
+  ret i64 %res
+}
+
+; AARCH64-CHECK: simulateWithDbgDeclare:
+; AARCH64-CHECK: movi d9, #0000000000000000
+; AARCH64-CHECK: bl lrand48
+; AARCH64-CHECK: mov x19, x0
+; AARCH64-CHECK: BB2_1:
+
+declare i64 @lrand48()
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.dbg.cu = !{!1}
+!llvm.module.flags = !{!3, !4}
+
+!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "test.ll", directory: ".")
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1)
+!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69)
+!7 = !DIExpression()
+!8 = !DILocation(line: 132, column: 2, scope: !5)

test/CodeGen/X86/selectiondag-order.ll

+; Check that debug intrinsics do not affect code generation.
+
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=X86-CHECK %s
+
+define i64 @simulate(<2 x i32> %a) {
+entry:
+  %rand = tail call i64 @lrand48()
+  br label %body
+
+body:                                        ; preds = %body, %entry
+  %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
+  %add = add <2 x i32> %0, %a
+  %rand1 = tail call i64 @lrand48() #3
+  %cmp = icmp eq i64 %rand1, 0
+  br i1 %cmp, label %end, label %body
+
+end:                                        ; preds = %body
+  %c = bitcast <2 x i32> %add to i64
+  %res = add i64 %rand, %c
+  ret i64 %res
+}
+
+; X86-CHECK: simulate:
+; X86-CHECK: movdqa  %xmm0, 16(%rsp)
+; X86-CHECK: pxor  %xmm0, %xmm0
+; X86-CHECK: movdqa  %xmm0, (%rsp)
+; X86-CHECK: callq  lrand48
+; X86-CHECK: movq  %rax, %rbx
+
+define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr  {
+entry:
+  %rand = tail call i64 @lrand48() #3
+  tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8
+  br label %body
+
+body:                                        ; preds = %body, %entry
+  %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
+  %add = add <2 x i32> %0, %a
+  %rand1 = tail call i64 @lrand48() #3
+  %cmp = icmp eq i64 %rand1, 0
+  br i1 %cmp, label %end, label %body
+
+end:                                        ; preds = %body
+  %c = bitcast <2 x i32> %add to i64
+  %res = add i64 %rand, %c
+  ret i64 %res
+}
+
+; X86-CHECK: simulateWithDebugIntrinsic:
+; X86-CHECK: movdqa  %xmm0, 16(%rsp)
+; X86-CHECK: pxor  %xmm0, %xmm0
+; X86-CHECK: movdqa  %xmm0, (%rsp)
+; X86-CHECK: callq  lrand48
+; X86-CHECK: movq  %rax, %rbx
+
+define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr  {
+entry:
+  %rand = tail call i64 @lrand48() #3
+  tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8
+  br label %body
+
+body:                                        ; preds = %body, %entry
+  %0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
+  %add = add <2 x i32> %0, %a
+  %rand1 = tail call i64 @lrand48() #3
+  %cmp = icmp eq i64 %rand1, 0
+  br i1 %cmp, label %end, label %body
+
+end:                                        ; preds = %body
+  %c = bitcast <2 x i32> %add to i64
+  %res = add i64 %rand, %c
+  ret i64 %res
+}
+
+; X86-CHECK: simulateWithDbgDeclare:
+; X86-CHECK: movdqa  %xmm0, 16(%rsp)
+; X86-CHECK: pxor  %xmm0, %xmm0
+; X86-CHECK: movdqa  %xmm0, (%rsp)
+; X86-CHECK: callq  lrand48
+; X86-CHECK: movq  %rax, %rbx
+
+declare i64 @lrand48()
+
+declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
+declare void @llvm.dbg.declare(metadata, metadata, metadata)
+
+!llvm.dbg.cu = !{!1}
+!llvm.module.flags = !{!3, !4}
+
+!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug)
+!2 = !DIFile(filename: "test.ll", directory: ".")
+!3 = !{i32 2, !"Dwarf Version", i32 4}
+!4 = !{i32 2, !"Debug Info Version", i32 3}
+!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1)
+!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69)
+!7 = !DIExpression()
+!8 = !DILocation(line: 132, column: 2, scope: !5)