[ELF] Refactor target errors

[evgeny777]

Summary

Prints locations for (most of) errors raised in Target.cpp file.

[ruiu]

ELF/Writer.cpp

1555

I think we should make OutputSections global, instead of doing a plumbing work to propagate information from Target to Writer.

[evgeny777]

ELF/Writer.cpp

1555

How about Buffer pointer? It isn't stored in OutputSection<ELFT>.
What do you think about saving buffer position in OutputSection<ELFT> and iterating over Symtab<ELFT>::Sections, instead of OutputSections ?

[ruiu]

ELF/Writer.cpp

1555

Interesting idea. Not sure if that's actually good at the moment, but it's worth a try.

[evgeny777]

Addressed review comments

[ruiu]

ELF/Target.cpp

61

I don't think we need a new error-ish function here. I'd define a function that returns the output location info as a string, then I could write like this.

error(getErrorLoc(Loc) + ": relocation " + toString(Type) + " out of range");

813

Then this can be

fatal(getErrorLoc(Loc) + ": unrecognized reloc " + Twine(Type));

ELF/Writer.cpp

1560–1561

Just return the return value of getLocation().

[evgeny777]

Addressed review comments

[ruiu]

LGTM. Nice!

ELF/Writer.cpp

1560

You can return IS->getLocation(Loc - ISLoc) + ": " here.

1564

and return "" here.

ELF/Writer.h

14

Do you need this?

ELF/OutputSections.h

public:
   void writeTo(uint8_t *Buf) override;
   void finalize() override;
   void assignOffsets() override;
   Kind getKind() const override { return Regular; }
   static bool classof(const OutputSectionBase *B) {
     return B->getKind() == Regular;
   }
   std::vector<InputSection<ELFT> *> Sections;
+
+  // Location in the output buffer.
+  uint8_t *Loc = nullptr;
 };
 
 template <class ELFT>
 class MergeOutputSection final : public OutputSectionBase {
   typedef typename ELFT::uint uintX_t;
 
 public:
   MergeOutputSection(StringRef Name, uint32_t Type, uintX_t Flags,

ELF/OutputSections.cpp

void fill(uint8_t *Buf, size_t Size, uint32_t Filler) {
   write32be(V, Filler);
   size_t I = 0;
   for (; I + 4 < Size; I += 4)
     memcpy(Buf + I, V, 4);
   memcpy(Buf + I, V, Size - I);
 }
 
 template <class ELFT> void OutputSection<ELFT>::writeTo(uint8_t *Buf) {
+  Loc = Buf;
   if (uint32_t Filler = Script<ELFT>::X->getFiller(this->Name))
     fill(Buf, this->Size, Filler);
 
   auto Fn = [=](InputSection<ELFT> *IS) { IS->writeTo(Buf); };
   if (Config->Threads)
     parallel_for_each(Sections.begin(), Sections.end(), Fn);
   else
     std::for_each(Sections.begin(), Sections.end(), Fn);

ELF/Target.cpp

 
 static void or32le(uint8_t *P, int32_t V) { write32le(P, read32le(P) | V); }
 static void or32be(uint8_t *P, int32_t V) { write32be(P, read32be(P) | V); }
 
 std::string toString(uint32_t Type) {
   return getELFRelocationTypeName(Config->EMachine, Type);
 }
 
-template <unsigned N> static void checkInt(int64_t V, uint32_t Type) {
+template <unsigned N>
+static void checkInt(uint8_t *Loc, int64_t V, uint32_t Type) {
   if (!isInt<N>(V))
-    error("relocation " + toString(Type) + " out of range");
+    errorAt(false, Loc, "relocation " + toString(Type) + " out of range");
 }
 
-template <unsigned N> static void checkUInt(uint64_t V, uint32_t Type) {
+template <unsigned N>
+static void checkUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
   if (!isUInt<N>(V))
-    error("relocation " + toString(Type) + " out of range");
+    errorAt(false, Loc, "relocation " + toString(Type) + " out of range");
 }
 
-template <unsigned N> static void checkIntUInt(uint64_t V, uint32_t Type) {
+template <unsigned N>
+static void checkIntUInt(uint8_t *Loc, uint64_t V, uint32_t Type) {
   if (!isInt<N>(V) && !isUInt<N>(V))
-    error("relocation " + toString(Type) + " out of range");
+    errorAt(false, Loc, "relocation " + toString(Type) + " out of range");
 }
 
-template <unsigned N> static void checkAlignment(uint64_t V, uint32_t Type) {
+template <unsigned N>
+static void checkAlignment(uint8_t *Loc, uint64_t V, uint32_t Type) {
   if ((V & (N - 1)) != 0)
-    error("improper alignment for relocation " + toString(Type));
+    errorAt(false, Loc, "improper alignment for relocation " + toString(Type));
 }
 
 namespace {
 class X86TargetInfo final : public TargetInfo {
 public:
   X86TargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
   uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
uint64_t X86TargetInfo::getImplicitAddend(const uint8_t *Buf,
   case R_386_PLT32:
   case R_386_TLS_LE:
     return read32le(Buf);
   }
 }
 
 void X86TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                 uint64_t Val) const {
-  checkInt<32>(Val, Type);
+  checkInt<32>(Loc, Val, Type);
   write32le(Loc, Val);
 }
 
 void X86TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
                                    uint64_t Val) const {
   // Convert
   //   leal x@tlsgd(, %ebx, 1),
   //   call __tls_get_addr@plt
if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {
     // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
     memcpy(Inst, "\x49\xc7", 2);
     *RegSlot = 0xc0 | Reg;
   } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {
     // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
     memcpy(Inst, "\x48\xc7", 2);
     *RegSlot = 0xc0 | Reg;
   } else {
-    fatal("R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
+    errorAt(true, Loc - 3,
+            "R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
   }
 
   // The original code used a PC relative relocation.
   // Need to compensate for the -4 it had in the addend.
   relocateOne(Loc, R_X86_64_TPOFF32, Val + 4);
 }
 
 template <class ELFT>
void X86_64TargetInfo<ELFT>::relaxTlsLdToLe(uint8_t *Loc, uint32_t Type,
   memcpy(Loc - 3, Inst, sizeof(Inst));
 }
 
 template <class ELFT>
 void X86_64TargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
                                          uint64_t Val) const {
   switch (Type) {
   case R_X86_64_32:
-    checkUInt<32>(Val, Type);
+    checkUInt<32>(Loc, Val, Type);
     write32le(Loc, Val);
     break;
   case R_X86_64_32S:
   case R_X86_64_TPOFF32:
   case R_X86_64_GOT32:
   case R_X86_64_GOTPCREL:
   case R_X86_64_GOTPCRELX:
   case R_X86_64_REX_GOTPCRELX:
   case R_X86_64_PC32:
   case R_X86_64_GOTTPOFF:
   case R_X86_64_PLT32:
   case R_X86_64_TLSGD:
   case R_X86_64_TLSLD:
   case R_X86_64_DTPOFF32:
   case R_X86_64_SIZE32:
-    checkInt<32>(Val, Type);
+    checkInt<32>(Loc, Val, Type);
     write32le(Loc, Val);
     break;
   case R_X86_64_64:
   case R_X86_64_DTPOFF64:
   case R_X86_64_SIZE64:
   case R_X86_64_PC64:
     write64le(Loc, Val);
     break;
   default:
-    fatal("unrecognized reloc " + Twine(Type));
+    errorAt(true, Loc, "unrecognized reloc " + Twine(Type));
   }
 }
 
 template <class ELFT>
 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type,
                                                 const uint8_t *Data,
                                                 RelExpr RelExpr) const {
   if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
void PPCTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
   case R_PPC_ADDR32:
   case R_PPC_REL32:
     write32be(Loc, Val);
     break;
   case R_PPC_REL24:
     or32be(Loc, Val & 0x3FFFFFC);
     break;
   default:
-    fatal("unrecognized reloc " + Twine(Type));
+    errorAt(true, Loc, "unrecognized reloc " + Twine(Type));
   }
 }
 
 RelExpr PPCTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   switch (Type) {
   case R_PPC_REL24:
   case R_PPC_REL32:
     return R_PC;

 void PPC64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                   uint64_t Val) const {
   // For a TOC-relative relocation, proceed in terms of the corresponding
   // ADDR16 relocation type.
   std::tie(Type, Val) = toAddr16Rel(Type, Val);
 
   switch (Type) {
   case R_PPC64_ADDR14: {
-    checkAlignment<4>(Val, Type);
+    checkAlignment<4>(Loc, Val, Type);
     // Preserve the AA/LK bits in the branch instruction
     uint8_t AALK = Loc[3];
     write16be(Loc + 2, (AALK & 3) | (Val & 0xfffc));
     break;
   }
   case R_PPC64_ADDR16:
-    checkInt<16>(Val, Type);
+    checkInt<16>(Loc, Val, Type);
     write16be(Loc, Val);
     break;
   case R_PPC64_ADDR16_DS:
-    checkInt<16>(Val, Type);
+    checkInt<16>(Loc, Val, Type);
     write16be(Loc, (read16be(Loc) & 3) | (Val & ~3));
     break;
   case R_PPC64_ADDR16_HA:
   case R_PPC64_REL16_HA:
     write16be(Loc, applyPPCHa(Val));
     break;
   case R_PPC64_ADDR16_HI:
   case R_PPC64_REL16_HI:
case R_PPC64_ADDR16_LO:
     write16be(Loc, applyPPCLo(Val));
     break;
   case R_PPC64_ADDR16_LO_DS:
   case R_PPC64_REL16_LO:
     write16be(Loc, (read16be(Loc) & 3) | (applyPPCLo(Val) & ~3));
     break;
   case R_PPC64_ADDR32:
   case R_PPC64_REL32:
-    checkInt<32>(Val, Type);
+    checkInt<32>(Loc, Val, Type);
     write32be(Loc, Val);
     break;
   case R_PPC64_ADDR64:
   case R_PPC64_REL64:
   case R_PPC64_TOC:
     write64be(Loc, Val);
     break;
   case R_PPC64_REL24: {
     uint32_t Mask = 0x03FFFFFC;
-    checkInt<24>(Val, Type);
+    checkInt<24>(Loc, Val, Type);
     write32be(Loc, (read32be(Loc) & ~Mask) | (Val & Mask));
     break;
   }
   default:
-    fatal("unrecognized reloc " + Twine(Type));
+    errorAt(true, Loc, "unrecognized reloc " + Twine(Type));
   }
 }
 
 AArch64TargetInfo::AArch64TargetInfo() {
   CopyRel = R_AARCH64_COPY;
   RelativeRel = R_AARCH64_RELATIVE;
   IRelativeRel = R_AARCH64_IRELATIVE;
   GotRel = R_AARCH64_GLOB_DAT;
static inline void updateAArch64Add(uint8_t *L, uint64_t Imm) {
   or32le(L, (Imm & 0xFFF) << 10);
 }
 
 void AArch64TargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
                                     uint64_t Val) const {
   switch (Type) {
   case R_AARCH64_ABS16:
   case R_AARCH64_PREL16:
-    checkIntUInt<16>(Val, Type);
+    checkIntUInt<16>(Loc, Val, Type);
     write16le(Loc, Val);
     break;
   case R_AARCH64_ABS32:
   case R_AARCH64_PREL32:
-    checkIntUInt<32>(Val, Type);
+    checkIntUInt<32>(Loc, Val, Type);
     write32le(Loc, Val);
     break;
   case R_AARCH64_ABS64:
   case R_AARCH64_PREL64:
     write64le(Loc, Val);
     break;
   case R_AARCH64_ADD_ABS_LO12_NC:
     // This relocation stores 12 bits and there's no instruction
     // to do it. Instead, we do a 32 bits store of the value
     // of r_addend bitwise-or'ed Loc. This assumes that the addend
     // bits in Loc are zero.
     or32le(Loc, (Val & 0xFFF) << 10);
     break;
   case R_AARCH64_ADR_GOT_PAGE:
   case R_AARCH64_ADR_PREL_PG_HI21:
   case R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21:
   case R_AARCH64_TLSDESC_ADR_PAGE21:
-    checkInt<33>(Val, Type);
+    checkInt<33>(Loc, Val, Type);
     updateAArch64Addr(Loc, Val >> 12);
     break;
   case R_AARCH64_ADR_PREL_LO21:
-    checkInt<21>(Val, Type);
+    checkInt<21>(Loc, Val, Type);
     updateAArch64Addr(Loc, Val);
     break;
   case R_AARCH64_CALL26:
   case R_AARCH64_JUMP26:
-    checkInt<28>(Val, Type);
+    checkInt<28>(Loc, Val, Type);
     or32le(Loc, (Val & 0x0FFFFFFC) >> 2);
     break;
   case R_AARCH64_CONDBR19:
-    checkInt<21>(Val, Type);
+    checkInt<21>(Loc, Val, Type);
     or32le(Loc, (Val & 0x1FFFFC) << 3);
     break;
   case R_AARCH64_LD64_GOT_LO12_NC:
   case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
   case R_AARCH64_TLSDESC_LD64_LO12_NC:
-    checkAlignment<8>(Val, Type);
+    checkAlignment<8>(Loc, Val, Type);
     or32le(Loc, (Val & 0xFF8) << 7);
     break;
   case R_AARCH64_LDST128_ABS_LO12_NC:
     or32le(Loc, (Val & 0x0FF8) << 6);
     break;
   case R_AARCH64_LDST16_ABS_LO12_NC:
     or32le(Loc, (Val & 0x0FFC) << 9);
     break;
case R_AARCH64_MOVW_UABS_G1_NC:
     break;
   case R_AARCH64_MOVW_UABS_G2_NC:
     or32le(Loc, (Val & 0xFFFF00000000) >> 27);
     break;
   case R_AARCH64_MOVW_UABS_G3:
     or32le(Loc, (Val & 0xFFFF000000000000) >> 43);
     break;
   case R_AARCH64_TSTBR14:
-    checkInt<16>(Val, Type);
+    checkInt<16>(Loc, Val, Type);
     or32le(Loc, (Val & 0xFFFC) << 3);
     break;
   case R_AARCH64_TLSLE_ADD_TPREL_HI12:
-    checkInt<24>(Val, Type);
+    checkInt<24>(Loc, Val, Type);
     updateAArch64Add(Loc, Val >> 12);
     break;
   case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
   case R_AARCH64_TLSDESC_ADD_LO12_NC:
     updateAArch64Add(Loc, Val);
     break;
   default:
-    fatal("unrecognized reloc " + Twine(Type));
+    errorAt(true, Loc, "unrecognized reloc " + Twine(Type));
   }
 }
 
 void AArch64TargetInfo::relaxTlsGdToLe(uint8_t *Loc, uint32_t Type,
                                        uint64_t Val) const {
   // TLSDESC Global-Dynamic relocation are in the form:
   //   adrp    x0, :tlsdesc:v             [R_AARCH64_TLSDESC_ADR_PAGE21]
   //   ldr     x1, [x0, #:tlsdesc_lo12:v  [R_AARCH64_TLSDESC_LD64_LO12_NC]
   //   add     x0, x0, :tlsdesc_los:v     [_AARCH64_TLSDESC_ADD_LO12_NC]
   //   .tlsdesccall                       [R_AARCH64_TLSDESC_CALL]
   //   blr     x1
   // And it can optimized to:
   //   movz    x0, #0x0, lsl #16
   //   movk    x0, #0x10
   //   nop
   //   nop
-  checkUInt<32>(Val, Type);
+  checkUInt<32>(Loc, Val, Type);
 
   switch (Type) {
   case R_AARCH64_TLSDESC_ADD_LO12_NC:
   case R_AARCH64_TLSDESC_CALL:
     write32le(Loc, 0xd503201f); // nop
     return;
   case R_AARCH64_TLSDESC_ADR_PAGE21:
     write32le(Loc, 0xd2a00000 | (((Val >> 16) & 0xffff) << 5)); // movz
case R_AARCH64_TLSDESC_LD64_LO12_NC:
     break;
   default:
     llvm_unreachable("unsupported relocation for TLS GD to LE relaxation");
   }
 }
 
 void AArch64TargetInfo::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
                                        uint64_t Val) const {
-  checkUInt<32>(Val, Type);
+  checkUInt<32>(Loc, Val, Type);
 
   if (Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21) {
     // Generate MOVZ.
     uint32_t RegNo = read32le(Loc) & 0x1f;
     write32le(Loc, (0xd2a00000 | RegNo) | (((Val >> 16) & 0xffff) << 5));
     return;
   }
   if (Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC) {
void AMDGPUTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
   case R_AMDGPU_ABS64:
     write64le(Loc, Val);
     break;
   case R_AMDGPU_GOTPCREL32_HI:
   case R_AMDGPU_REL32_HI:
     write32le(Loc, Val >> 32);
     break;
   default:
-    fatal("unrecognized reloc " + Twine(Type));
+    errorAt(true, Loc, "unrecognized reloc " + Twine(Type));
   }
 }
 
 RelExpr AMDGPUTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   switch (Type) {
   case R_AMDGPU_ABS32:
   case R_AMDGPU_ABS64:
     return R_ABS;
void ARMTargetInfo::relocateOne(uint8_t *Loc, uint32_t Type,
   case R_ARM_TLS_GD32:
   case R_ARM_TLS_IE32:
   case R_ARM_TLS_LDM32:
   case R_ARM_TLS_LDO32:
   case R_ARM_TLS_LE32:
     write32le(Loc, Val);
     break;
   case R_ARM_PREL31:
-    checkInt<31>(Val, Type);
+    checkInt<31>(Loc, Val, Type);
     write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
     break;
   case R_ARM_CALL:
     // R_ARM_CALL is used for BL and BLX instructions, depending on the
     // value of bit 0 of Val, we must select a BL or BLX instruction
     if (Val & 1) {
       // If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
       // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
-      checkInt<26>(Val, Type);
+      checkInt<26>(Loc, Val, Type);
       write32le(Loc, 0xfa000000 |                    // opcode
                          ((Val & 2) << 23) |         // H
                          ((Val >> 2) & 0x00ffffff)); // imm24
       break;
     }
     if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
       // BLX (always unconditional) instruction to an ARM Target, select an
       // unconditional BL.
       write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
   // fall through as BL encoding is shared with B
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
-    checkInt<26>(Val, Type);
+    checkInt<26>(Loc, Val, Type);
     write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
     break;
   case R_ARM_THM_JUMP11:
-    checkInt<12>(Val, Type);
+    checkInt<12>(Loc, Val, Type);
     write16le(Loc, (read32le(Loc) & 0xf800) | ((Val >> 1) & 0x07ff));
     break;
   case R_ARM_THM_JUMP19:
     // Encoding T3: Val = S:J2:J1:imm6:imm11:0
-    checkInt<21>(Val, Type);
+    checkInt<21>(Loc, Val, Type);
     write16le(Loc,
               (read16le(Loc) & 0xfbc0) |   // opcode cond
                   ((Val >> 10) & 0x0400) | // S
                   ((Val >> 12) & 0x003f)); // imm6
     write16le(Loc + 2,
               0x8000 |                    // opcode
                   ((Val >> 8) & 0x0800) | // J2
                   ((Val >> 5) & 0x2000) | // J1
                   ((Val >> 1) & 0x07ff)); // imm11
     break;
   case R_ARM_THM_CALL:
     // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
     // value of bit 0 of Val, we must select a BL or BLX instruction
     if ((Val & 1) == 0) {
       // Ensure BLX destination is 4-byte aligned. As BLX instruction may
       // only be two byte aligned. This must be done before overflow check
       Val = alignTo(Val, 4);
     }
     // Bit 12 is 0 for BLX, 1 for BL
     write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
   // Fall through as rest of encoding is the same as B.W
   case R_ARM_THM_JUMP24:
     // Encoding B  T4, BL T1, BLX T2: Val = S:I1:I2:imm10:imm11:0
     // FIXME: Use of I1 and I2 require v6T2ops
-    checkInt<25>(Val, Type);
+    checkInt<25>(Loc, Val, Type);
     write16le(Loc,
               0xf000 |                     // opcode
                   ((Val >> 14) & 0x0400) | // S
                   ((Val >> 12) & 0x03ff)); // imm10
     write16le(Loc + 2,
               (read16le(Loc + 2) & 0xd000) |                  // opcode
                   (((~(Val >> 10)) ^ (Val >> 11)) & 0x2000) | // J1
                   (((~(Val >> 11)) ^ (Val >> 13)) & 0x0800) | // J2
                   ((Val >> 1) & 0x07ff));                     // imm11
     break;
   case R_ARM_MOVW_ABS_NC:
   case R_ARM_MOVW_PREL_NC:
     write32le(Loc, (read32le(Loc) & ~0x000f0fff) | ((Val & 0xf000) << 4) |
                        (Val & 0x0fff));
     break;
   case R_ARM_MOVT_ABS:
   case R_ARM_MOVT_PREL:
-    checkInt<32>(Val, Type);
+    checkInt<32>(Loc, Val, Type);
     write32le(Loc, (read32le(Loc) & ~0x000f0fff) |
                        (((Val >> 16) & 0xf000) << 4) | ((Val >> 16) & 0xfff));
     break;
   case R_ARM_THM_MOVT_ABS:
   case R_ARM_THM_MOVT_PREL:
     // Encoding T1: A = imm4:i:imm3:imm8
-    checkInt<32>(Val, Type);
+    checkInt<32>(Loc, Val, Type);
     write16le(Loc,
               0xf2c0 |                     // opcode
                   ((Val >> 17) & 0x0400) | // i
                   ((Val >> 28) & 0x000f)); // imm4
     write16le(Loc + 2,
               (read16le(Loc + 2) & 0x8f00) | // opcode
                   ((Val >> 12) & 0x7000) |   // imm3
                   ((Val >> 16) & 0x00ff));   // imm8
     break;
   case R_ARM_THM_MOVW_ABS_NC:
   case R_ARM_THM_MOVW_PREL_NC:
     // Encoding T3: A = imm4:i:imm3:imm8
     write16le(Loc,
               0xf240 |                     // opcode
                   ((Val >> 1) & 0x0400) |  // i
                   ((Val >> 12) & 0x000f)); // imm4
     write16le(Loc + 2,
               (read16le(Loc + 2) & 0x8f00) | // opcode
                   ((Val << 4) & 0x7000) |    // imm3
                   (Val & 0x00ff));           // imm8
     break;
   default:
-    fatal("unrecognized reloc " + Twine(Type));
+    errorAt(true, Loc, "unrecognized reloc " + Twine(Type));
   }
 }
 
 uint64_t ARMTargetInfo::getImplicitAddend(const uint8_t *Buf,
                                           uint32_t Type) const {
   switch (Type) {
   default:
     return 0;
static int64_t getPcRelocAddend(const uint8_t *Loc) {
   return SignExtend64<BSIZE + SHIFT>((Instr & Mask) << SHIFT);
 }
 
 template <endianness E, uint8_t BSIZE, uint8_t SHIFT>
 static void applyMipsPcReloc(uint8_t *Loc, uint32_t Type, uint64_t V) {
   uint32_t Mask = 0xffffffff >> (32 - BSIZE);
   uint32_t Instr = read32<E>(Loc);
   if (SHIFT > 0)
-    checkAlignment<(1 << SHIFT)>(V, Type);
-  checkInt<BSIZE + SHIFT>(V, Type);
+    checkAlignment<(1 << SHIFT)>(Loc, V, Type);
+  checkInt<BSIZE + SHIFT>(Loc, V, Type);
   write32<E>(Loc, (Instr & ~Mask) | ((V >> SHIFT) & Mask));
 }
 
 template <endianness E> static void writeMipsHi16(uint8_t *Loc, uint64_t V) {
   uint32_t Instr = read32<E>(Loc);
   uint16_t Res = ((V + 0x8000) >> 16) & 0xffff;
   write32<E>(Loc, (Instr & 0xffff0000) | Res);
 }
case R_MIPS_PC21_S2:
     return getPcRelocAddend<E, 21, 2>(Buf);
   case R_MIPS_PC26_S2:
     return getPcRelocAddend<E, 26, 2>(Buf);
   case R_MIPS_PC32:
     return getPcRelocAddend<E, 32, 0>(Buf);
   }
 }
 
-static std::pair<uint32_t, uint64_t> calculateMipsRelChain(uint32_t Type,
-                                                           uint64_t Val) {
+static std::pair<uint32_t, uint64_t>
+calculateMipsRelChain(uint8_t *Loc, uint32_t Type, uint64_t Val) {
   // MIPS N64 ABI packs multiple relocations into the single relocation
   // record. In general, all up to three relocations can have arbitrary
   // types. In fact, Clang and GCC uses only a few combinations. For now,
   // we support two of them. That is allow to pass at least all LLVM
   // test suite cases.
   // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
   // <any relocation> / R_MIPS_64 / R_MIPS_NONE
   // The first relocation is a 'real' relocation which is calculated
   // using the corresponding symbol's value. The second and the third
   // relocations used to modify result of the first one: extend it to
   // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
   // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
   uint32_t Type2 = (Type >> 8) & 0xff;
   uint32_t Type3 = (Type >> 16) & 0xff;
   if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
     return std::make_pair(Type, Val);
   if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
     return std::make_pair(Type2, Val);
   if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))
     return std::make_pair(Type3, -Val);
-  error("unsupported relocations combination " + Twine(Type));
+  errorAt(false, Loc, "unsupported relocations combination " + Twine(Type));
   return std::make_pair(Type & 0xff, Val);
 }
 
 template <class ELFT>
 void MipsTargetInfo<ELFT>::relocateOne(uint8_t *Loc, uint32_t Type,
                                        uint64_t Val) const {
   const endianness E = ELFT::TargetEndianness;
   // Thread pointer and DRP offsets from the start of TLS data area.
   // https://www.linux-mips.org/wiki/NPTL
   if (Type == R_MIPS_TLS_DTPREL_HI16 || Type == R_MIPS_TLS_DTPREL_LO16 ||
       Type == R_MIPS_TLS_DTPREL32 || Type == R_MIPS_TLS_DTPREL64)
     Val -= 0x8000;
   else if (Type == R_MIPS_TLS_TPREL_HI16 || Type == R_MIPS_TLS_TPREL_LO16 ||
            Type == R_MIPS_TLS_TPREL32 || Type == R_MIPS_TLS_TPREL64)
     Val -= 0x7000;
   if (ELFT::Is64Bits || Config->MipsN32Abi)
-    std::tie(Type, Val) = calculateMipsRelChain(Type, Val);
+    std::tie(Type, Val) = calculateMipsRelChain(Loc, Type, Val);
   switch (Type) {
   case R_MIPS_32:
   case R_MIPS_GPREL32:
   case R_MIPS_TLS_DTPREL32:
   case R_MIPS_TLS_TPREL32:
     write32<E>(Loc, Val);
     break;
   case R_MIPS_64:
   case R_MIPS_TLS_DTPREL64:
   case R_MIPS_TLS_TPREL64:
     write64<E>(Loc, Val);
     break;
   case R_MIPS_26:
     write32<E>(Loc, (read32<E>(Loc) & ~0x3ffffff) | ((Val >> 2) & 0x3ffffff));
     break;
   case R_MIPS_GOT_DISP:
   case R_MIPS_GOT_PAGE:
   case R_MIPS_GOT16:
   case R_MIPS_GPREL16:
   case R_MIPS_TLS_GD:
   case R_MIPS_TLS_LDM:
-    checkInt<16>(Val, Type);
+    checkInt<16>(Loc, Val, Type);
   // fallthrough
   case R_MIPS_CALL16:
   case R_MIPS_CALL_LO16:
   case R_MIPS_GOT_LO16:
   case R_MIPS_GOT_OFST:
   case R_MIPS_LO16:
   case R_MIPS_PCLO16:
   case R_MIPS_TLS_DTPREL_LO16:
case R_MIPS_PC21_S2:
     break;
   case R_MIPS_PC26_S2:
     applyMipsPcReloc<E, 26, 2>(Loc, Type, Val);
     break;
   case R_MIPS_PC32:
     applyMipsPcReloc<E, 32, 0>(Loc, Type, Val);
     break;
   default:
-    fatal("unrecognized reloc " + Twine(Type));
+    errorAt(true, Loc, "unrecognized reloc " + Twine(Type));
   }
 }
 
 template <class ELFT>
 bool MipsTargetInfo<ELFT>::usesOnlyLowPageBits(uint32_t Type) const {
   return Type == R_MIPS_LO16 || Type == R_MIPS_GOT_OFST;
 }
 }
 }

ELF/Writer.h

 //===- Writer.h -------------------------------------------------*- C++ -*-===//
 //
 //                             The LLVM Linker
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLD_ELF_WRITER_H
 #define LLD_ELF_WRITER_H
 
 #include "llvm/ADT/StringRef.h"
+#include "llvm/ADT/Twine.h"
 #include <cstdint>
 #include <memory>
 
 namespace lld {
 namespace elf {
 class InputFile;
 class OutputSectionBase;
 template <class ELFT> class InputSectionBase;

 template <class ELFT> void reportDiscarded(InputSectionBase<ELFT> *IS);
 
 template <class ELFT> uint32_t getMipsEFlags();
 
 uint8_t getMipsFpAbiFlag(uint8_t OldFlag, uint8_t NewFlag,
                          llvm::StringRef FileName);
 
 bool isMipsN32Abi(const InputFile *F);
+void errorAt(bool Fatal, uint8_t *Loc, const llvm::Twine &Msg);
 }
 }
 
 #endif

ELF/Writer.cpp

if (!In<ELFT>::BuildId || !In<ELFT>::BuildId->OutSec)
     return;
 
   // Compute a hash of all sections of the output file.
   uint8_t *Start = Buffer->getBufferStart();
   uint8_t *End = Start + FileSize;
   In<ELFT>::BuildId->writeBuildId({Start, End});
 }
 
+template <class ELFT> static std::string getErrorLocation(uint8_t *Loc) {
+  std::string ErrLoc;
+
+  for (InputSectionData *D : Symtab<ELFT>::X->Sections) {
+    auto *IS = dyn_cast_or_null<InputSection<ELFT>>(D);
+    if (!IS || !IS->OutSec)
+      continue;
+
+    uint8_t *ISLoc = cast<OutputSection<ELFT>>(IS->OutSec)->Loc + IS->OutSecOff;
+    if (ISLoc <= Loc && ISLoc + IS->getSize() > Loc) {
+      ErrLoc = getLocation(*IS, Loc - ISLoc);
+      break;
+    }
+  }
+  return ErrLoc;
+}
+
+void elf::errorAt(bool Fatal, uint8_t *Loc, const Twine &Msg) {
+  std::string ErrLoc;
+  switch (Config->EKind) {
+  case ELF32LEKind:
+    ErrLoc = getErrorLocation<ELF32LE>(Loc);
+    break;
+  case ELF32BEKind:
+    ErrLoc = getErrorLocation<ELF32BE>(Loc);
+    break;
+  case ELF64LEKind:
+    ErrLoc = getErrorLocation<ELF64LE>(Loc);
+    break;
+  case ELF64BEKind:
+    ErrLoc = getErrorLocation<ELF64BE>(Loc);
+    break;
+  default:
+    llvm_unreachable("unknown ELF type");
+  }
+
+  if (Fatal)
+    fatal(ErrLoc.empty() ? Msg : ErrLoc + ": " + Msg.str());
+  else
+    error(ErrLoc.empty() ? Msg : ErrLoc + ": " + Msg.str());
+}
+
 template void elf::writeResult<ELF32LE>();
 template void elf::writeResult<ELF32BE>();
 template void elf::writeResult<ELF64LE>();
 template void elf::writeResult<ELF64BE>();
 
 template struct elf::PhdrEntry<ELF32LE>;
 template struct elf::PhdrEntry<ELF32BE>;
 template struct elf::PhdrEntry<ELF64LE>;

test/ELF/mips-align-err.s

 # REQUIRES: mips
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux %s -o %t.o \
 # RUN:         -mcpu=mips32r6
 # RUN: llvm-mc -filetype=obj -triple=mips-unknown-linux \
 # RUN:         -mcpu=mips32r6 %S/Inputs/mips-align-err.s -o %t2.o
 # RUN: not ld.lld %t.o %t2.o -o %t.exe 2>&1 | FileCheck %s
-# CHECK: improper alignment for relocation R_MIPS_PC16
+# CHECK: {{.*}}:(.text+0x1): improper alignment for relocation R_MIPS_PC16
 
         .globl  __start
 __start:
 .zero 1
         beqc      $5, $6, _foo            # R_MIPS_PC16

test/ELF/x86-64-reloc-error.s

 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %S/Inputs/x86-64-reloc-error.s -o %tabs
 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t
 // RUN: not ld.lld -shared %tabs %t -o %t2 2>&1 | FileCheck %s
 // REQUIRES: x86
 
   movl $big, %edx
   movq $foo - 0x1000000000000, %rdx
 
-# CHECK: R_X86_64_32 out of range
-# CHECK: R_X86_64_32S out of range
+# CHECK: {{.*}}:(.text+0x1): relocation R_X86_64_32 out of range
+# CHECK: {{.*}}:(.text+0x8): relocation R_X86_64_32S out of range

test/ELF/x86-64-reloc-range.s

 // RUN: llvm-mc %s -o %t.o -triple x86_64-pc-linux -filetype=obj
 // RUN: not ld.lld %t.o -o %t.so -shared 2>&1 | FileCheck %s
 
-// CHECK: relocation R_X86_64_PC32 out of range
+// CHECK: {{.*}}:(.text+0x3): relocation R_X86_64_PC32 out of range
 // CHECK-NOT: relocation
 
         lea     foo(%rip), %rax
         lea     foo(%rip), %rax
 
         .hidden foo
         .bss
         .zero 0x7fffe007
 foo: