[ELF] Refactor getDynRel to print error location

[evgeny777]

Summary

Errors in getDynRel are quite common, so it might be worth printing exact place of error.

[ruiu]

ELF/Relocations.cpp

719

I think we don't put a period at end of a sentence in error messages.

722

Add a blank line between code and comment.

ELF/Target.cpp

697–698

Probably unintended change.

739–740

Ditto

821–824

Ditto

842

Ditto (and so on)

ELF/Target.h

29–31

The meaning of the second return value is not very clear. How about this? We can add Target::isAbsRel(uint32_t). If it returns true, we should report an error. Then I think we don't need to modify getDynRel.

[evgeny777]

ELF/Target.h

29–31

isAbsRel is a bit confusing (in position independent code RelExpr may be R_GOT_PC as well). How about isPICRel ?

[evgeny777]

Addressed review comments

[ruiu]

LGTM with these comments addressed.

ELF/Relocations.cpp

716

We have Config->Pic, so it should be named isPicRel.

722

ping

ELF/Target.cpp

1270–1271

You can just return Type because R_AARCH64_ABS32 was just a dummy value to return something in an error condition.

2001

Remove () after return.

2003–2006

This is I think just a dummy value, too.

ELF/Relocations.cpp

if (needsPlt(Expr) || Expr == R_THUNK_ABS || Expr == R_THUNK_PC ||
       // If the produced value is a constant, we just remember to write it
       // when outputting this section. We also have to do it if the format
       // uses Elf_Rel, since in that case the written value is the addend.
       if (Constant || !RelTy::IsRela)
         C.Relocations.push_back({Expr, Type, Offset, Addend, &Body});
     } else {
       // We don't know anything about the finaly symbol. Just ask the dynamic
       // linker to handle the relocation for us.
-      AddDyn({Target->getDynRel(Type), &C, Offset, false, &Body, Addend});
+      const auto &P = Target->getDynRel(Type);
+      if (!P.second)
+        error(getLocation(C, Offset) + ": relocation " + getRelName(Type) +
+              " cannot be used against shared object; recompile with -fPIC.");
+
+      AddDyn({P.first, &C, Offset, false, &Body, Addend});
       // MIPS ABI turns using of GOT and dynamic relocations inside out.
       // While regular ABI uses dynamic relocations to fill up GOT entries
       // MIPS ABI requires dynamic linker to fills up GOT entries using
       // specially sorted dynamic symbol table. This affects even dynamic
       // relocations against symbols which do not require GOT entries
       // creation explicitly, i.e. do not have any GOT-relocations. So if
       // a preemptible symbol has a dynamic relocation we anyway have
       // to create a GOT entry for it.
       // If a non-preemptible symbol has a dynamic relocation against it,

ELF/Target.h

 class InputFile;
 class SymbolBody;
 
 class TargetInfo {
 public:
   virtual bool isTlsInitialExecRel(uint32_t Type) const;
   virtual bool isTlsLocalDynamicRel(uint32_t Type) const;
   virtual bool isTlsGlobalDynamicRel(uint32_t Type) const;
-  virtual uint32_t getDynRel(uint32_t Type) const { return Type; }
+  virtual std::pair<uint32_t, bool> getDynRel(uint32_t Type) const {
+    return {Type, true};
+  }
   virtual void writeGotPltHeader(uint8_t *Buf) const {}
   virtual void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {};
   virtual uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const;
 
   // If lazy binding is supported, the first entry of the PLT has code
   // to call the dynamic linker to resolve PLT entries the first time
   // they are called. This function writes that code.
   virtual void writePltHeader(uint8_t *Buf) const {}

ELF/Target.cpp

if (!isInt<N>(V) && !isUInt<N>(V))
     error("relocation " + getRelName(Type) + " out of range");
 }
 
 template <unsigned N> static void checkAlignment(uint64_t V, uint32_t Type) {
   if ((V & (N - 1)) != 0)
     error("improper alignment for relocation " + getRelName(Type));
 }
 
-static void errorDynRel(uint32_t Type) {
-  error("relocation " + getRelName(Type) +
-        " cannot be used against shared object; recompile with -fPIC.");
-}
-
 namespace {
 class X86TargetInfo final : public TargetInfo {
 public:
   X86TargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
   uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
   void writeGotPltHeader(uint8_t *Buf) const override;
-  uint32_t getDynRel(uint32_t Type) const override;
+  std::pair<uint32_t, bool> getDynRel(uint32_t Type) const override;
   bool isTlsLocalDynamicRel(uint32_t Type) const override;
   bool isTlsGlobalDynamicRel(uint32_t Type) const override;
   bool isTlsInitialExecRel(uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 
   RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
                           RelExpr Expr) const override;
   void relaxTlsGdToIe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   void relaxTlsGdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   void relaxTlsIeToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   void relaxTlsLdToLe(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 };
 
 template <class ELFT> class X86_64TargetInfo final : public TargetInfo {
 public:
   X86_64TargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
-  uint32_t getDynRel(uint32_t Type) const override;
+  std::pair<uint32_t, bool> getDynRel(uint32_t Type) const override;
   bool isTlsLocalDynamicRel(uint32_t Type) const override;
   bool isTlsGlobalDynamicRel(uint32_t Type) const override;
   bool isTlsInitialExecRel(uint32_t Type) const override;
   void writeGotPltHeader(uint8_t *Buf) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 };
 
 class AArch64TargetInfo final : public TargetInfo {
 public:
   AArch64TargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
-  uint32_t getDynRel(uint32_t Type) const override;
+  std::pair<uint32_t, bool> getDynRel(uint32_t Type) const override;
   bool isTlsInitialExecRel(uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   bool usesOnlyLowPageBits(uint32_t Type) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   RelExpr adjustRelaxExpr(uint32_t Type, const uint8_t *Data,
public:
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
 };
 
 class ARMTargetInfo final : public TargetInfo {
 public:
   ARMTargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
-  uint32_t getDynRel(uint32_t Type) const override;
+  std::pair<uint32_t, bool> getDynRel(uint32_t Type) const override;
   uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
   bool isTlsLocalDynamicRel(uint32_t Type) const override;
   bool isTlsGlobalDynamicRel(uint32_t Type) const override;
   bool isTlsInitialExecRel(uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File,
                        const SymbolBody &S) const override;
   void relocateOne(uint8_t *Loc, uint32_t Type, uint64_t Val) const override;
 };
 
 template <class ELFT> class MipsTargetInfo final : public TargetInfo {
 public:
   MipsTargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
   uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
-  uint32_t getDynRel(uint32_t Type) const override;
+  std::pair<uint32_t, bool> getDynRel(uint32_t Type) const override;
   bool isTlsLocalDynamicRel(uint32_t Type) const override;
   bool isTlsGlobalDynamicRel(uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;
   RelExpr getThunkExpr(RelExpr Expr, uint32_t RelocType, const InputFile &File,
                        const SymbolBody &S) const override;

 }
 
 void X86TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {
   // Entries in .got.plt initially points back to the corresponding
   // PLT entries with a fixed offset to skip the first instruction.
   write32le(Buf, S.getPltVA<ELF32LE>() + 6);
 }
 
-uint32_t X86TargetInfo::getDynRel(uint32_t Type) const {
+std::pair<uint32_t, bool> X86TargetInfo::getDynRel(uint32_t Type) const {
   if (Type == R_386_TLS_LE)
-    return R_386_TLS_TPOFF;
+    return {R_386_TLS_TPOFF, true};
   if (Type == R_386_TLS_LE_32)
-    return R_386_TLS_TPOFF32;
-  return Type;
+    return {R_386_TLS_TPOFF32, true};
+  return {Type, true};
 }
 
 bool X86TargetInfo::isTlsGlobalDynamicRel(uint32_t Type) const {
   return Type == R_386_TLS_GD;
 }
 
 bool X86TargetInfo::isTlsLocalDynamicRel(uint32_t Type) const {
   return Type == R_386_TLS_LDO_32 || Type == R_386_TLS_LDM;
void X86_64TargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
   memcpy(Buf, Inst, sizeof(Inst));
 
   write32le(Buf + 2, GotEntryAddr - PltEntryAddr - 6);
   write32le(Buf + 7, Index);
   write32le(Buf + 12, -Index * PltEntrySize - PltHeaderSize - 16);
 }
 
 template <class ELFT>
-uint32_t X86_64TargetInfo<ELFT>::getDynRel(uint32_t Type) const {
+std::pair<uint32_t, bool>
+X86_64TargetInfo<ELFT>::getDynRel(uint32_t Type) const {
   if (Type == R_X86_64_PC32 || Type == R_X86_64_32)
-    errorDynRel(Type);
-  return Type;
+    return {Type, false};
+  return {Type, true};
 }
 
 template <class ELFT>
 bool X86_64TargetInfo<ELFT>::isTlsInitialExecRel(uint32_t Type) const {
   return Type == R_X86_64_GOTTPOFF;
 }
 
 template <class ELFT>
void X86_64TargetInfo<ELFT>::relaxTlsGdToIe(uint8_t *Loc, uint32_t Type,
   // to
   //   mov %fs:0x0,%rax
   //   addq x@tpoff,%rax
   const uint8_t Inst[] = {
       0x64, 0x48, 0x8b, 0x04, 0x25, 0x00, 0x00, 0x00, 0x00, // mov %fs:0x0,%rax
       0x48, 0x03, 0x05, 0x00, 0x00, 0x00, 0x00              // addq x@tpoff,%rax
   };
   memcpy(Loc - 4, Inst, sizeof(Inst));
-  // Both code sequences are PC relatives, but since we are moving the constant
+  // Both code sequences are PC relatives, but since we are moving the
+  // constant
   // forward by 8 bytes we have to subtract the value by 8.
   relocateOne(Loc + 8, R_X86_64_PC32, Val - 8);
 }
 
 // In some conditions, R_X86_64_GOTTPOFF relocation can be optimized to
 // R_X86_64_TPOFF32 so that it does not use GOT.
 template <class ELFT>
 void X86_64TargetInfo<ELFT>::relaxTlsIeToLe(uint8_t *Loc, uint32_t Type,
if (memcmp(Inst, "\x48\x03\x25", 3) == 0) {
     // "movq foo@gottpoff(%rip),%r[8-15]" -> "movq $foo,%r[8-15]"
     memcpy(Inst, "\x49\xc7", 2);
     *RegSlot = 0xc0 | Reg;
   } else if (memcmp(Inst, "\x48\x8b", 2) == 0) {
     // "movq foo@gottpoff(%rip),%reg" -> "movq $foo,%reg"
     memcpy(Inst, "\x48\xc7", 2);
     *RegSlot = 0xc0 | Reg;
   } else {
-    fatal("R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions only");
+    fatal("R_X86_64_GOTTPOFF must be used in MOVQ or ADDQ instructions "
+          "only");
   }
 
   // The original code used a PC relative relocation.
   // Need to compensate for the -4 it had in the addend.
   relocateOne(Loc, R_X86_64_TPOFF32, Val + 4);
 }
 
 template <class ELFT>

 RelExpr X86_64TargetInfo<ELFT>::adjustRelaxExpr(uint32_t Type,
                                                 const uint8_t *Data,
                                                 RelExpr RelExpr) const {
   if (Type != R_X86_64_GOTPCRELX && Type != R_X86_64_REX_GOTPCRELX)
     return RelExpr;
   const uint8_t Op = Data[-2];
   const uint8_t ModRm = Data[-1];
   // FIXME: When PIC is disabled and foo is defined locally in the
-  // lower 32 bit address space, memory operand in mov can be converted into
-  // immediate operand. Otherwise, mov must be changed to lea. We support only
+  // lower 32 bit address space, memory operand in mov can be converted
+  // into
+  // immediate operand. Otherwise, mov must be changed to lea. We support
+  // only
   // latter relaxation at this moment.
   if (Op == 0x8b)
     return R_RELAX_GOT_PC;
   // Relax call and jmp.
   if (Op == 0xff && (ModRm == 0x15 || ModRm == 0x25))
     return R_RELAX_GOT_PC;
 
   // Relaxation of test, adc, add, and, cmp, or, sbb, sub, xor.
   // If PIC then no relaxation is available.
   // We also don't relax test/binop instructions without REX byte,
   // they are 32bit operations and not common to have.
   assert(Type == R_X86_64_REX_GOTPCRELX);
   return Config->Pic ? RelExpr : R_RELAX_GOT_PC_NOPIC;
 }
 
 // A subset of relaxations can only be applied for no-PIC. This method
-// handles such relaxations. Instructions encoding information was taken from:
+// handles such relaxations. Instructions encoding information was taken
+// from:
 // "Intel 64 and IA-32 Architectures Software Developer's Manual V2"
 // (http://www.intel.com/content/dam/www/public/us/en/documents/manuals/
 //    64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf)
 template <class ELFT>
 void X86_64TargetInfo<ELFT>::relaxGotNoPic(uint8_t *Loc, uint64_t Val,
                                            uint8_t Op, uint8_t ModRm) const {
   const uint8_t Rex = Loc[-3];
   // Convert "test %reg, foo@GOTPCREL(%rip)" to "test $foo, %reg".
   if (Op == 0x85) {
     // See "TEST-Logical Compare" (4-428 Vol. 2B),
     // TEST r/m64, r64 uses "full" ModR / M byte (no opcode extension).
 
     // ModR/M byte has form XX YYY ZZZ, where
     // YYY is MODRM.reg(register 2), ZZZ is MODRM.rm(register 1).
     // XX has different meanings:
     // 00: The operand's memory address is in reg1.
-    // 01: The operand's memory address is reg1 + a byte-sized displacement.
-    // 10: The operand's memory address is reg1 + a word-sized displacement.
+    // 01: The operand's memory address is reg1 + a byte-sized
+    // displacement.
+    // 10: The operand's memory address is reg1 + a word-sized
+    // displacement.
     // 11: The operand is reg1 itself.
     // If an instruction requires only one operand, the unused reg2 field
     // holds extra opcode bits rather than a register code
     // 0xC0 == 11 000 000 binary.
     // 0x38 == 00 111 000 binary.
     // We transfer reg2 to reg1 here as operand.
     // See "2.1.3 ModR/M and SIB Bytes" (Vol. 2A 2-3).
     Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3; // ModR/M byte.
 
     // Change opcode from TEST r/m64, r64 to TEST r/m64, imm32
     // See "TEST-Logical Compare" (4-428 Vol. 2B).
     Loc[-2] = 0xf7;
 
     // Move R bit to the B bit in REX byte.
     // REX byte is encoded as 0100WRXB, where
     // 0100 is 4bit fixed pattern.
     // REX.W When 1, a 64-bit operand size is used. Otherwise, when 0, the
-    //   default operand size is used (which is 32-bit for most but not all
+    //   default operand size is used (which is 32-bit for most but not
+    //   all
     //   instructions).
     // REX.R This 1-bit value is an extension to the MODRM.reg field.
     // REX.X This 1-bit value is an extension to the SIB.index field.
     // REX.B This 1-bit value is an extension to the MODRM.rm field or the
     // SIB.base field.
     // See "2.2.1.2 More on REX Prefix Fields " (2-8 Vol. 2A).
     Loc[-3] = (Rex & ~0x4) | (Rex & 0x4) >> 2;
     relocateOne(Loc, R_X86_64_PC32, Val);
     return;
   }
 
-  // If we are here then we need to relax the adc, add, and, cmp, or, sbb, sub
+  // If we are here then we need to relax the adc, add, and, cmp, or, sbb,
+  // sub
   // or xor operations.
 
   // Convert "binop foo@GOTPCREL(%rip), %reg" to "binop $foo, %reg".
   // Logic is close to one for test instruction above, but we also
   // write opcode extension here, see below for details.
   Loc[-1] = 0xc0 | (ModRm & 0x38) >> 3 | (Op & 0x3c); // ModR/M byte.
 
   // Primary opcode is 0x81, opcode extension is one of:
if (Op != 0xff) {
     // for the old -4 addend.
     assert(!Config->Pic);
     relaxGotNoPic(Loc, Val + 4, Op, ModRm);
     return;
   }
 
   // Convert call/jmp instructions.
   if (ModRm == 0x15) {
-    // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call foo".
-    // Instead we convert to "addr32 call foo" where addr32 is an instruction
+    // ABI says we can convert "call *foo@GOTPCREL(%rip)" to "nop; call
+    // foo".
+    // Instead we convert to "addr32 call foo" where addr32 is an
+    // instruction
     // prefix. That makes result expression to be a single instruction.
     Loc[-2] = 0x67; // addr32 prefix
     Loc[-1] = 0xe8; // call
     relocateOne(Loc, R_X86_64_PC32, Val);
     return;
   }
 
   // Convert "jmp *foo@GOTPCREL(%rip)" to "jmp foo; nop".
PPC64TargetInfo::PPC64TargetInfo() {
   PltHeaderSize = 0;
 
   // We need 64K pages (at least under glibc/Linux, the loader won't
   // set different permissions on a finer granularity than that).
   MaxPageSize = 65536;
 
   // The PPC64 ELF ABI v1 spec, says:
   //
-  //   It is normally desirable to put segments with different characteristics
+  //   It is normally desirable to put segments with different
+  //   characteristics
   //   in separate 256 Mbyte portions of the address space, to give the
-  //   operating system full paging flexibility in the 64-bit address space.
+  //   operating system full paging flexibility in the 64-bit address
+  //   space.
   //
-  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64 linkers
+  // And because the lowest non-zero 256M boundary is 0x10000000, PPC64
+  // linkers
   // use 0x10000000 as the starting address.
   DefaultImageBase = 0x10000000;
 }
 
 static uint64_t PPC64TocOffset = 0x8000;
 
 uint64_t getPPC64TocBase() {
-  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order. The
-  // TOC starts where the first of these sections starts. We always create a
-  // .got when we see a relocation that uses it, so for us the start is always
+  // The TOC consists of sections .got, .toc, .tocbss, .plt in that order.
+  // The
+  // TOC starts where the first of these sections starts. We always create
+  // a
+  // .got when we see a relocation that uses it, so for us the start is
+  // always
   // the .got.
   uint64_t TocVA = In<ELF64BE>::Got->getVA();
 
   // Per the ppc64-elf-linux ABI, The TOC base is TOC value plus 0x8000
   // thus permitting a full 64 Kbytes segment. Note that the glibc startup
   // code (crt1.o) assumes that you can get from the TOC base to the
-  // start of the .toc section with only a single (signed) 16-bit relocation.
+  // start of the .toc section with only a single (signed) 16-bit
+  // relocation.
   return TocVA + PPC64TocOffset;
 }
 
 RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   switch (Type) {
   default:
     return R_ABS;
   case R_PPC64_TOC16:
RelExpr PPC64TargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   }
 }
 
 void PPC64TargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
                                uint64_t PltEntryAddr, int32_t Index,
                                unsigned RelOff) const {
   uint64_t Off = GotEntryAddr - getPPC64TocBase();
 
-  // FIXME: What we should do, in theory, is get the offset of the function
-  // descriptor in the .opd section, and use that as the offset from %r2 (the
-  // TOC-base pointer). Instead, we have the GOT-entry offset, and that will
+  // FIXME: What we should do, in theory, is get the offset of the
+  // function
+  // descriptor in the .opd section, and use that as the offset from %r2
+  // (the
+  // TOC-base pointer). Instead, we have the GOT-entry offset, and that
+  // will
   // be a pointer to the function descriptor in the .opd section. Using
-  // this scheme is simpler, but requires an extra indirection per PLT dispatch.
+  // this scheme is simpler, but requires an extra indirection per PLT
+  // dispatch.
 
   write32be(Buf, 0xf8410028);                       // std %r2, 40(%r1)
   write32be(Buf + 4, 0x3d620000 | applyPPCHa(Off)); // addis %r11, %r2, X@ha
   write32be(Buf + 8, 0xe98b0000 | applyPPCLo(Off)); // ld %r12, X@l(%r11)
   write32be(Buf + 12, 0xe96c0000);                  // ld %r11,0(%r12)
   write32be(Buf + 16, 0x7d6903a6);                  // mtctr %r11
   write32be(Buf + 20, 0xe84c0008);                  // ld %r2,8(%r12)
   write32be(Buf + 24, 0xe96c0010);                  // ld %r11,16(%r12)
AArch64TargetInfo::AArch64TargetInfo() {
   TlsDescRel = R_AARCH64_TLSDESC;
   TlsGotRel = R_AARCH64_TLS_TPREL64;
   GotEntrySize = 8;
   GotPltEntrySize = 8;
   PltEntrySize = 16;
   PltHeaderSize = 32;
   MaxPageSize = 65536;
 
-  // It doesn't seem to be documented anywhere, but tls on aarch64 uses variant
+  // It doesn't seem to be documented anywhere, but tls on aarch64 uses
+  // variant
   // 1 of the tls structures and the tcb size is 16.
   TcbSize = 16;
 }
 
 RelExpr AArch64TargetInfo::getRelExpr(uint32_t Type,
                                       const SymbolBody &S) const {
   switch (Type) {
   default:
bool AArch64TargetInfo::usesOnlyLowPageBits(uint32_t Type) const {
   }
 }
 
 bool AArch64TargetInfo::isTlsInitialExecRel(uint32_t Type) const {
   return Type == R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 ||
          Type == R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC;
 }
 
-uint32_t AArch64TargetInfo::getDynRel(uint32_t Type) const {
+std::pair<uint32_t, bool> AArch64TargetInfo::getDynRel(uint32_t Type) const {
   if (Type == R_AARCH64_ABS32 || Type == R_AARCH64_ABS64)
-    return Type;
-  // Keep it going with a dummy value so that we can find more reloc errors.
-  errorDynRel(Type);
-  return R_AARCH64_ABS32;
+    return {Type, true};
+  return {R_AARCH64_ABS32, false};
 }
 
 void AArch64TargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
   write64le(Buf, In<ELF64LE>::Plt->getVA());
 }
 
 static uint64_t getAArch64Page(uint64_t Expr) {
   return Expr & (~static_cast<uint64_t>(0xFFF));
 }
 
 void AArch64TargetInfo::writePltHeader(uint8_t *Buf) const {
   const uint8_t PltData[] = {
       0xf0, 0x7b, 0xbf, 0xa9, // stp  x16, x30, [sp,#-16]!
       0x10, 0x00, 0x00, 0x90, // adrp  x16, Page(&(.plt.got[2]))
-      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16, Offset(&(.plt.got[2]))]
+      0x11, 0x02, 0x40, 0xf9, // ldr  x17, [x16,
+                              // Offset(&(.plt.got[2]))]
       0x10, 0x02, 0x00, 0x91, // add  x16, x16, Offset(&(.plt.got[2]))
       0x20, 0x02, 0x1f, 0xd6, // br x17
       0x1f, 0x20, 0x03, 0xd5, // nop
       0x1f, 0x20, 0x03, 0xd5, // nop
       0x1f, 0x20, 0x03, 0xd5  // nop
   };
   memcpy(Buf, PltData, sizeof(PltData));
 
RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   case R_ARM_THM_MOVT_PREL:
     return R_PC;
   case R_ARM_NONE:
     return R_HINT;
   case R_ARM_TLS_LE32:
     return R_TLS;
   }
 }
-
-uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const {
+std::pair<uint32_t, bool> ARMTargetInfo::getDynRel(uint32_t Type) const {
   if (Type == R_ARM_TARGET1 && !Config->Target1Rel)
-    return R_ARM_ABS32;
+    return {R_ARM_ABS32, true};
   if (Type == R_ARM_ABS32)
-    return Type;
-  // Keep it going with a dummy value so that we can find more reloc errors.
-  errorDynRel(Type);
-  return R_ARM_ABS32;
+    return {Type, true};
+  // Keep it going with a dummy value so that we can find more reloc
+  // errors.
+  return {R_ARM_ABS32, false};
 }
 
 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
   write32le(Buf, In<ELF32LE>::Plt->getVA());
 }
 
 void ARMTargetInfo::writePltHeader(uint8_t *Buf) const {
   const uint8_t PltData[] = {
       0x04, 0xe0, 0x2d, 0xe5, //     str lr, [sp,#-4]!
       0x04, 0xe0, 0x9f, 0xe5, //     ldr lr, L2
       0x0e, 0xe0, 0x8f, 0xe0, // L1: add lr, pc, lr
       0x08, 0xf0, 0xbe, 0xe5, //     ldr pc, [lr, #8]
       0x00, 0x00, 0x00, 0x00, // L2: .word   &(.got.plt) - L1 - 8
   };
   memcpy(Buf, PltData, sizeof(PltData));
   uint64_t GotPlt = In<ELF32LE>::GotPlt->getVA();
   uint64_t L1 = In<ELF32LE>::Plt->getVA() + 8;
   write32le(Buf + 16, GotPlt - L1 - 8);
 }
 
 void ARMTargetInfo::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
                              uint64_t PltEntryAddr, int32_t Index,
                              unsigned RelOff) const {
   // FIXME: Using simple code sequence with simple relocations.
-  // There is a more optimal sequence but it requires support for the group
+  // There is a more optimal sequence but it requires support for the
+  // group
   // relocations. See ELF for the ARM Architecture Appendix A.3
   const uint8_t PltData[] = {
       0x04, 0xc0, 0x9f, 0xe5, //     ldr ip, L2
       0x0f, 0xc0, 0x8c, 0xe0, // L1: add ip, ip, pc
       0x00, 0xf0, 0x9c, 0xe5, //     ldr pc, [ip]
       0x00, 0x00, 0x00, 0x00, // L2: .word   Offset(&(.plt.got) - L1 - 8
   };
   memcpy(Buf, PltData, sizeof(PltData));
RelExpr ARMTargetInfo::getThunkExpr(RelExpr Expr, uint32_t RelocType,
   case R_ARM_JUMP24:
     // Source is ARM, all PLT entries are ARM so no interworking required.
     // Otherwise we need to interwork if Symbol has bit 0 set (Thumb).
     if (Expr == R_PC && ((S.getVA<ELF32LE>() & 1) == 1))
       return R_THUNK_PC;
     break;
   case R_ARM_THM_JUMP19:
   case R_ARM_THM_JUMP24:
-    // Source is Thumb, all PLT entries are ARM so interworking is required.
+    // Source is Thumb, all PLT entries are ARM so interworking is
+    // required.
     // Otherwise we need to interwork if Symbol has bit 0 clear (ARM).
     if (Expr == R_PLT_PC)
       return R_THUNK_PLT_PC;
     if ((S.getVA<ELF32LE>() & 1) == 0)
       return R_THUNK_PC;
     break;
   }
   return Expr;
if (Val & 1) {
       // The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
       checkInt<26>(Val, Type);
       write32le(Loc, 0xfa000000 |                    // opcode
                          ((Val & 2) << 23) |         // H
                          ((Val >> 2) & 0x00ffffff)); // imm24
       break;
     }
     if ((read32le(Loc) & 0xfe000000) == 0xfa000000)
-      // BLX (always unconditional) instruction to an ARM Target, select an
+      // BLX (always unconditional) instruction to an ARM Target, select
+      // an
       // unconditional BL.
       write32le(Loc, 0xeb000000 | (read32le(Loc) & 0x00ffffff));
   // fall through as BL encoding is shared with B
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
     checkInt<26>(Val, Type);
     write32le(Loc, (read32le(Loc) & ~0x00ffffff) | ((Val >> 2) & 0x00ffffff));
write16le(Loc,
                   ((Val >> 12) & 0x003f)); // imm6
     write16le(Loc + 2,
               0x8000 |                    // opcode
                   ((Val >> 8) & 0x0800) | // J2
                   ((Val >> 5) & 0x2000) | // J1
                   ((Val >> 1) & 0x07ff)); // imm11
     break;
   case R_ARM_THM_CALL:
-    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
+    // R_ARM_THM_CALL is used for BL and BLX instructions, depending on
+    // the
     // value of bit 0 of Val, we must select a BL or BLX instruction
     if ((Val & 1) == 0) {
       // Ensure BLX destination is 4-byte aligned. As BLX instruction may
       // only be two byte aligned. This must be done before overflow check
       Val = alignTo(Val, 4);
     }
     // Bit 12 is 0 for BLX, 1 for BL
     write16le(Loc + 2, (read16le(Loc + 2) & ~0x1000) | (Val & 1) << 12);
RelExpr MipsTargetInfo<ELFT>::getRelExpr(uint32_t Type,
   case R_MIPS_TLS_GD:
     return R_MIPS_TLSGD;
   case R_MIPS_TLS_LDM:
     return R_MIPS_TLSLD;
   }
 }
 
 template <class ELFT>
-uint32_t MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const {
+std::pair<uint32_t, bool> MipsTargetInfo<ELFT>::getDynRel(uint32_t Type) const {
   if (Type == R_MIPS_32 || Type == R_MIPS_64)
-    return RelativeRel;
-  // Keep it going with a dummy value so that we can find more reloc errors.
-  errorDynRel(Type);
-  return R_MIPS_32;
+    return {RelativeRel, true};
+  // Keep it going with a dummy value so that we can find more reloc
+  // errors.
+  return {R_MIPS_32, false};
 }
 
 template <class ELFT>
 bool MipsTargetInfo<ELFT>::isTlsLocalDynamicRel(uint32_t Type) const {
   return Type == R_MIPS_TLS_LDM;
 }
 
 template <class ELFT>
void MipsTargetInfo<ELFT>::writePlt(uint8_t *Buf, uint64_t GotEntryAddr,
   writeMipsLo16<E>(Buf + 4, GotEntryAddr);
   writeMipsLo16<E>(Buf + 12, GotEntryAddr);
 }
 
 template <class ELFT>
 RelExpr MipsTargetInfo<ELFT>::getThunkExpr(RelExpr Expr, uint32_t Type,
                                            const InputFile &File,
                                            const SymbolBody &S) const {
-  // Any MIPS PIC code function is invoked with its address in register $t9.
+  // Any MIPS PIC code function is invoked with its address in register
+  // $t9.
   // So if we have a branch instruction from non-PIC code to the PIC one
   // we cannot make the jump directly and need to create a small stubs
   // to save the target function address.
-  // See page 3-38 ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
+  // See page 3-38
+  // ftp://www.linux-mips.org/pub/linux/mips/doc/ABI/mipsabi.pdf
   if (Type != R_MIPS_26)
     return Expr;
   auto *F = dyn_cast<ELFFileBase<ELFT>>(&File);
   if (!F)
     return Expr;
   // If current file has PIC code, LA25 stub is not required.
   if (F->getObj().getHeader()->e_flags & EF_MIPS_PIC)
     return Expr;
static std::pair<uint32_t, uint64_t> calculateMipsRelChain(uint32_t Type,
   // types. In fact, Clang and GCC uses only a few combinations. For now,
   // we support two of them. That is allow to pass at least all LLVM
   // test suite cases.
   // <any relocation> / R_MIPS_SUB / R_MIPS_HI16 | R_MIPS_LO16
   // <any relocation> / R_MIPS_64 / R_MIPS_NONE
   // The first relocation is a 'real' relocation which is calculated
   // using the corresponding symbol's value. The second and the third
   // relocations used to modify result of the first one: extend it to
-  // 64-bit, extract high or low part etc. For details, see part 2.9 Relocation
+  // 64-bit, extract high or low part etc. For details, see part 2.9
+  // Relocation
   // at the https://dmz-portal.mips.com/mw/images/8/82/007-4658-001.pdf
   uint32_t Type2 = (Type >> 8) & 0xff;
   uint32_t Type3 = (Type >> 16) & 0xff;
   if (Type2 == R_MIPS_NONE && Type3 == R_MIPS_NONE)
     return std::make_pair(Type, Val);
   if (Type2 == R_MIPS_64 && Type3 == R_MIPS_NONE)
     return std::make_pair(Type2, Val);
   if (Type2 == R_MIPS_SUB && (Type3 == R_MIPS_HI16 || Type3 == R_MIPS_LO16))

test/ELF/aarch64-fpic-abs16.s

 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-freebsd %s -o %t.o
 // RUN: not ld.lld -shared %t.o -o %t.so 2>&1 | FileCheck %s
-// CHECK: relocation R_AARCH64_ABS16 cannot be used against shared object; recompile with -fPIC.
+// CHECK: {{.*}}:(.data+0x0): relocation R_AARCH64_ABS16 cannot be used against shared object; recompile with -fPIC.
 
 .data
   .hword foo

test/ELF/aarch64-fpic-prel16.s

 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-freebsd %s -o %t.o
 // RUN: not ld.lld -shared %t.o -o %t.so 2>&1 | FileCheck %s
-// CHECK: relocation R_AARCH64_PREL16 cannot be used against shared object; recompile with -fPIC.
+// CHECK: {{.*}}:(.data+0x0): relocation R_AARCH64_PREL16 cannot be used against shared object; recompile with -fPIC.
 
 .data
   .hword foo - .

test/ELF/aarch64-fpic-prel32.s

 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-freebsd %s -o %t.o
 // RUN: not ld.lld -shared %t.o -o %t.so 2>&1 | FileCheck %s
-// CHECK: relocation R_AARCH64_PREL32 cannot be used against shared object; recompile with -fPIC.
+// CHECK: {{.*}}:(.data+0x0): relocation R_AARCH64_PREL32 cannot be used against shared object; recompile with -fPIC.
 
 .data
   .word foo - .

test/ELF/aarch64-fpic-prel64.s

 // REQUIRES: aarch64
 // RUN: llvm-mc -filetype=obj -triple=aarch64-none-freebsd %s -o %t.o
 // RUN: not ld.lld -shared %t.o -o %t.so 2>&1 | FileCheck %s
-// CHECK: relocation R_AARCH64_PREL64 cannot be used against shared object; recompile with -fPIC.
+// CHECK: {{.*}}:(.data+0x0): relocation R_AARCH64_PREL64 cannot be used against shared object; recompile with -fPIC.
 
 .data
   .xword foo - .

test/ELF/x86-64-dyn-rel-error.s

 // REQUIRES: x86
 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/shared.s -o %t2.o
 // RUN: ld.lld %t2.o -shared -o %t2.so
 // RUN: not ld.lld %t.o %t2.so -o %t 2>&1 | FileCheck %s
 
         .global _start
 _start:
         .data
         .long bar
 
-// CHECK: R_X86_64_32 cannot be used against shared object; recompile with -fPIC.
+// CHECK: {{.*}}:(.data+0x0): relocation R_X86_64_32 cannot be used against shared object; recompile with -fPIC.

test/ELF/x86-64-dyn-rel-error2.s

 // REQUIRES: x86
 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %s -o %t.o
 // RUN: llvm-mc -filetype=obj -triple=x86_64-pc-linux %p/Inputs/shared.s -o %t2.o
 // RUN: ld.lld %t2.o -shared -o %t2.so
 // RUN: not ld.lld %t.o %t2.so -o %t 2>&1 | FileCheck %s
 
         .global _start
 _start:
         .data
         .long bar - .
 
-// CHECK: R_X86_64_PC32 cannot be used against shared object; recompile with -fPIC.
+// CHECK: {{.*}}:(.data+0x0): relocation R_X86_64_PC32 cannot be used against shared object; recompile with -fPIC.

test/ELF/x86-64-reloc-32-fpic.s

 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: not ld.lld -shared %t.o -o %t.so 2>&1 | FileCheck %s
-# CHECK: relocation R_X86_64_32 cannot be used against shared object; recompile with -fPIC.
+# CHECK: {{.*}}:(.data+0x0): relocation R_X86_64_32 cannot be used against shared object; recompile with -fPIC.
 
 .data
 .long _shared

test/ELF/x86-64-reloc-pc32-fpic.s

 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-unknown-linux %s -o %t.o
 # RUN: not ld.lld -shared %t.o -o %t.so 2>&1 | FileCheck %s
-# CHECK: relocation R_X86_64_PC32 cannot be used against shared object; recompile with -fPIC.
+# CHECK: {{.*}}:(.data+0x1): relocation R_X86_64_PC32 cannot be used against shared object; recompile with -fPIC.
 
 .data
 call _shared