[X86][AVX512] Instructions fixups

[coby]

Summary

Some instructions were missing, other implemented falsely. this patch aims at amending those issues. full list:

vcvtps2pd
vcvtudq2pd
vcvtps2qq
vcvttps2qq
vcvtps2uqq
vcvttps2uqq

variants are:

[Dst]XMM(zero-masked/merge-masked/unmasked)
[Src]Mem64

Differential Revision: https://reviews.llvm.org/D26799

[craig.topper]

lib/Target/X86/X86InstrAVX512.td

0–1

Shouldn't this be i64mem too? The only difference between VCVTDQ2PD and VCVTUDQ2PD is that one is signed and the other is unsigned. They should have the same load size.

[coby]

lib/Target/X86/X86InstrAVX512.td

0–1

Note we are altering (in this case - preserving) the AVX512(f,vl) variants alone, which are to load from an xmm-width memory locations (according to formal documentation).
quad-word instances are restricted to AVX/SSE.
OTOH, VCVTUDQ2PD, is indeed spec'd to load from a quad-word.

[craig.topper]

That has to be a mistake in the documentation. It seems very unlikely they would have changed the behavior between SSE/AVX and AVX-512. The description under the table in the Intel docs does mention 64-bit memory location.

"EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit
memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand
is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX
embedded rounding is ignored."

[delena]

lib/Target/X86/X86InstrAVX512.td

0–1

I also think that it should be i64mem for XMM-destination form and i128mem for YMM-destination form.
So, in this case I agree with Craig. The bug is in documentation.

[coby]

lib/Target/X86/X86InstrAVX512.td

0–1

Then i'll refer it as such. will make amends.

[coby]

vcvtdq2pd --> now sets to load from a i64mem.
added appropriate test cases.

lib/Target/X86/X86InstrAVX512.td

 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //

 //===----------------------------------------------------------------------===//
 // AVX-512  Vector convert from signed/unsigned integer to float/double
 //          and from float/double to signed/unsigned integer
 //===----------------------------------------------------------------------===//
 
 multiclass avx512_vcvt_fp<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                          X86VectorVTInfo _Src, SDNode OpNode,
                          string Broadcast = _.BroadcastStr,
-                         string Alias = ""> {
+                         string Alias = "", X86MemOperand MemOp = _Src.MemOp> {
 
   defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _Src.RC:$src), OpcodeStr, "$src", "$src",
                          (_.VT (OpNode (_Src.VT _Src.RC:$src)))>, EVEX;
 
   defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
-                         (ins _Src.MemOp:$src), OpcodeStr#Alias, "$src", "$src",
+                         (ins MemOp:$src), OpcodeStr#Alias, "$src", "$src",
                          (_.VT (OpNode (_Src.VT
                              (bitconvert (_Src.LdFrag addr:$src)))))>, EVEX;
 
   defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
                          (ins _Src.ScalarMemOp:$src), OpcodeStr,
                          "${src}"##Broadcast, "${src}"##Broadcast,
                          (_.VT (OpNode (_Src.VT
                                   (X86VBroadcast (_Src.ScalarLdFrag addr:$src)))

 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fpextend>,
              avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
                                 X86vfpextRnd>, EVEX_V512;
   }
   let Predicates = [HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
-                               X86vfpext, "{1to2}">, EVEX_V128;
+                               X86vfpext, "{1to2}", "", f64mem>, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fpextend>,
                                      EVEX_V256;
   }
 }
 
 // Truncate Double to Float
 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
   let Predicates = [HasAVX512] in {
multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
                            SDNode OpNode128> {
   // No rounding in this op
   let Predicates = [HasAVX512] in
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i32x_info, OpNode>,
                                      EVEX_V512;
 
   let Predicates = [HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4i32x_info,
-                                     OpNode128, "{1to2}">, EVEX_V128;
+                                     OpNode128, "{1to2}", "", i64mem>, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i32x_info, OpNode>,
                                      EVEX_V256;
   }
 }
 
 // Convert Signed/Unsigned Doubleword to Float
 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
                            SDNode OpNodeRnd> {
let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
              avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
                                OpNodeRnd>, EVEX_V512;
   }
   let Predicates = [HasDQI, HasVLX] in {
     // Explicitly specified broadcast string, since we take only 2 elements
     // from v4f32x_info source
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
-                               "{1to2}">, EVEX_V128;
+                               "{1to2}", "", f64mem>, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
                                EVEX_V256;
   }
 }
 
 // Convert Float to Signed/Unsigned Quardword with truncation
 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
              avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
                                OpNodeRnd>, EVEX_V512;
   }
   let Predicates = [HasDQI, HasVLX] in {
     // Explicitly specified broadcast string, since we take only 2 elements
     // from v4f32x_info source
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
-                               "{1to2}">, EVEX_V128;
+                               "{1to2}", "", f64mem>, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
                                EVEX_V256;
   }
 }
 
 // Convert Signed/Unsigned Quardword to Float
 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
                     (!cast<Instruction>(NAME # "Z128rm") VR128X:$dst, i128mem:$src), 0>;
     def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
                     (!cast<Instruction>(NAME # "Z256rr") VR128X:$dst, VR256X:$src), 0>;
     def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
                     (!cast<Instruction>(NAME # "Z256rm") VR128X:$dst, i256mem:$src), 0>;
   }
 }
 
-defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>, XS,
-                                EVEX_CD8<32, CD8VH>;
+defm VCVTDQ2PD : avx512_cvtdq2pd<0xE6, "vcvtdq2pd", sint_to_fp, X86cvtdq2pd>,
+                                XS, EVEX_CD8<32, CD8VH>;
 
 defm VCVTDQ2PS : avx512_cvtdq2ps<0x5B, "vcvtdq2ps", sint_to_fp,
                                 X86VSintToFpRnd>,
                                 PS, EVEX_CD8<32, CD8VF>;
 
 defm VCVTTPS2DQ : avx512_cvttps2dq<0x5B, "vcvttps2dq", fp_to_sint,
                                 X86cvttp2siRnd>,
                                 XS, EVEX_CD8<32, CD8VF>;

test/MC/X86/intel-syntax-x86-64-avx512f_vl.s

 
 // CHECK: vcvtuqq2ps xmm16, ymmword ptr [rax]
 // CHECK: encoding: [0x62,0xe1,0xff,0x28,0x7a,0x00]
           vcvtuqq2ps xmm16, ymmword ptr [rax]
 
 // CHECK: vcvtuqq2ps xmm16, ymmword ptr [rax]
 // CHECK: encoding: [0x62,0xe1,0xff,0x28,0x7a,0x00]
           vcvtuqq2psy xmm16, ymmword ptr [rax]
+
+// CHECK: vcvtps2pd xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7c,0x8a,0x5a,0x49,0x10]
+          vcvtps2pd xmm1 {k2} {z}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtps2pd xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7c,0x0a,0x5a,0x49,0x10]
+          vcvtps2pd xmm1 {k2}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtudq2pd xmm2 {k2} {z}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x8a,0x7a,0x51,0x10]
+          vcvtudq2pd xmm2 {k2} {z}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtudq2pd xmm2 {k2}, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x0a,0x7a,0x51,0x10]
+          vcvtudq2pd xmm2 {k2}, qword ptr [rcx+0x80]
+
+// CHECK: vcvtudq2pd xmm2, qword ptr [rcx + 128]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x08,0x7a,0x51,0x10]
+          vcvtudq2pd xmm2, qword ptr [rcx+0x80]
+
+// CHECK: vcvtdq2pd xmm2 {k1}, qword ptr [rcx]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x09,0xe6,0x11]
+          vcvtdq2pd xmm2 {k1}, qword ptr [rcx]
+
+// CHECK: vcvtdq2pd xmm2 {k1} {z}, qword ptr [rcx]
+// CHECK: encoding: [0x62,0xf1,0x7e,0x89,0xe6,0x11]
+          vcvtdq2pd xmm2 {k1} {z}, qword ptr [rcx]
+

test/MC/X86/intel-syntax-x86-avx512dq_vl.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown -mcpu=knl -mattr=+avx512vl -mattr=+avx512dq -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
+
+// CHECK:  vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x8a,0x7b,0x51,0x10]
+          vcvtps2qq xmm2 {k2} {z}, qword ptr [rcx + 0x80]
+
+// CHECK:  vcvtps2qq xmm2 {k2}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x0a,0x7b,0x51,0x10]
+          vcvtps2qq xmm2 {k2}, qword ptr [rcx + 0x80]
+
+// CHECK:  vcvtps2qq xmm2, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x08,0x7b,0x51,0x10]
+          vcvtps2qq xmm2, qword ptr [rcx + 0x80]
+
+// CHECK:  vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x8a,0x7a,0x49,0x10]
+          vcvttps2qq xmm1 {k2} {z}, qword ptr [rcx + 0x80]
+
+// CHECK:  vcvttps2qq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x0a,0x7a,0x49,0x10]
+          vcvttps2qq xmm1 {k2}, qword ptr [rcx + 0x80]
+
+// CHECK:  vcvttps2qq xmm1, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x08,0x7a,0x49,0x10]
+          vcvttps2qq xmm1, qword ptr [rcx + 0x80]
+
+// CHECK:  vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x8a,0x79,0x49,0x10]
+          vcvtps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+
+// CHECK:  vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x0a,0x79,0x49,0x10]
+          vcvtps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+
+// CHECK:  vcvtps2uqq xmm1, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x08,0x79,0x49,0x10]
+          vcvtps2uqq xmm1, qword ptr [rcx + 128]
+
+// CHECK:  vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x8a,0x78,0x49,0x10]
+          vcvttps2uqq xmm1 {k2} {z}, qword ptr [rcx + 128]
+
+// CHECK:  vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x0a,0x78,0x49,0x10]
+          vcvttps2uqq xmm1 {k2}, qword ptr [rcx + 128]
+
+// CHECK:  vcvttps2uqq xmm1, qword ptr [rcx + 128]
+// CHECK:  encoding: [0x62,0xf1,0x7d,0x08,0x78,0x49,0x10]
+          vcvttps2uqq xmm1, qword ptr [rcx + 128]