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Differential D26714

[AMDGPU] Handle f16 select{_cc}
ClosedPublic

Authored by kzhuravl on Nov 15 2016, 3:57 PM.

Details

Reviewers
• tstellarAMD
arsenm
Commits
rG2a87a42035a1: [AMDGPU] Handle f16 select{_cc}
rL287074: [AMDGPU] Handle f16 select{_cc}
Summary
  • Select select to v_cndmask_b32
  • Expand select_cc
  • Refactor patterns

Diff Detail

Event Timeline

kzhuravl updated this revision to Diff 78093.Nov 15 2016, 3:57 PM
kzhuravl retitled this revision from to [AMDGPU] Handle f16 select{_cc}.
kzhuravl updated this object.
kzhuravl added reviewers: • tstellarAMD, arsenm.
kzhuravl added subscribers: b-sumner, llvm-commits.
Herald edited edge metadata. · View Herald TranscriptNov 15 2016, 3:57 PM
Herald added subscribers: tony-tye, yaxunl, nhaehnle, wdng. · View Herald Transcript
arsenm accepted this revision.Nov 15 2016, 4:07 PM
arsenm edited edge metadata.

LGTM

lib/Target/AMDGPU/SIISelLowering.cpp
292

Also should have a test for BR_CC, which probably also needs this

This revision is now accepted and ready to land.Nov 15 2016, 4:07 PM
Closed by commit rL287074: [AMDGPU] Handle f16 select{_cc} (authored by kzhuravl). · Explain WhyNov 15 2016, 7:26 PM
This revision was automatically updated to reflect the committed changes.
kzhuravl added inline comments.Nov 15 2016, 7:26 PM
lib/Target/AMDGPU/SIISelLowering.cpp
292

Thanks, I will do it in a follow up patch.

kzhuravl mentioned this in D26732: [AMDGPU] Expand `br_cc` for f16.Nov 15 2016, 9:11 PM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
1 line
22 lines
5 lines
test/
CodeGen/
AMDGPU/
322 lines

Diff 78093

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 283 Lines • ▼ Show 20 Lines if (Subtarget->has16BitInsts()) {
setOperationAction(ISD::STORE, MVT::f16, Promote); setOperationAction(ISD::STORE, MVT::f16, Promote);
AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16); AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
// F16 - VOP1 Actions. // F16 - VOP1 Actions.
setOperationAction(ISD::FCOS, MVT::f16, Promote); setOperationAction(ISD::FCOS, MVT::f16, Promote);
setOperationAction(ISD::FSIN, MVT::f16, Promote); setOperationAction(ISD::FSIN, MVT::f16, Promote);
// F16 - VOP2 Actions. // F16 - VOP2 Actions.
setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
arsenmUnsubmitted
Not Done
ReplyInline Actions

Also should have a test for BR_CC, which probably also needs this

arsenm: Also should have a test for BR_CC, which probably also needs this
kzhuravlAuthorUnsubmitted
Not Done
ReplyInline Actions

Thanks, I will do it in a follow up patch.

kzhuravl: Thanks, I will do it in a follow up patch.
setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
setOperationAction(ISD::FMINNUM, MVT::f16, Legal); setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
setOperationAction(ISD::FDIV, MVT::f16, Promote); setOperationAction(ISD::FDIV, MVT::f16, Promote);
// F16 - VOP3 Actions. // F16 - VOP3 Actions.
setOperationAction(ISD::FMA, MVT::f16, Legal); setOperationAction(ISD::FMA, MVT::f16, Legal);
if (!Subtarget->hasFP16Denormals()) if (!Subtarget->hasFP16Denormals())
setOperationAction(ISD::FMAD, MVT::f16, Legal); setOperationAction(ISD::FMAD, MVT::f16, Legal);
▲ Show 20 Lines • Show All 3,965 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 462 Lines • ▼ Show 20 Linesdef : Pat <
(f16 (uint_to_fp i32:$src)), (f16 (uint_to_fp i32:$src)),
(V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 $src)) (V_CVT_F16_F32_e32 (V_CVT_F32_U32_e32 $src))
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VOP2 Patterns // VOP2 Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass SelectPat<ValueType vt, Instruction inst> {
def : Pat < def : Pat <
(i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), (vt (select i1:$src0, vt:$src1, vt:$src2)),
(V_BCNT_U32_B32_e64 $popcnt, $val) (inst $src2, $src1, $src0)
>; >;
}
defm : SelectPat<i16, V_CNDMASK_B32_e64>;
defm : SelectPat<i32, V_CNDMASK_B32_e64>;
defm : SelectPat<f16, V_CNDMASK_B32_e64>;
defm : SelectPat<f32, V_CNDMASK_B32_e64>;
def : Pat < def : Pat <
(i32 (select i1:$src0, i32:$src1, i32:$src2)), (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)),
(V_CNDMASK_B32_e64 $src2, $src1, $src0) (V_BCNT_U32_B32_e64 $popcnt, $val)
>; >;
// Pattern for V_MAC_F16 // Pattern for V_MAC_F16
def : Pat < def : Pat <
(f16 (fmad (VOP3NoMods0 f16:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), (f16 (fmad (VOP3NoMods0 f16:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
(VOP3NoMods f16:$src1, i32:$src1_modifiers), (VOP3NoMods f16:$src1, i32:$src1_modifiers),
(VOP3NoMods f16:$src2, i32:$src2_modifiers))), (VOP3NoMods f16:$src2, i32:$src2_modifiers))),
(V_MAC_F16_e64 $src0_modifiers, $src0, $src1_modifiers, $src1, (V_MAC_F16_e64 $src0_modifiers, $src0, $src1_modifiers, $src1,
▲ Show 20 Lines • Show All 498 Lines • ▼ Show 20 Lines
def : Pat < def : Pat <
(i32 (bswap i32:$a)), (i32 (bswap i32:$a)),
(V_BFI_B32 (S_MOV_B32 (i32 0x00ff00ff)), (V_BFI_B32 (S_MOV_B32 (i32 0x00ff00ff)),
(V_ALIGNBIT_B32 $a, $a, (i32 24)), (V_ALIGNBIT_B32 $a, $a, (i32 24)),
(V_ALIGNBIT_B32 $a, $a, (i32 8))) (V_ALIGNBIT_B32 $a, $a, (i32 8)))
>; >;
def : Pat <
(f32 (select i1:$src2, f32:$src1, f32:$src0)),
(V_CNDMASK_B32_e64 $src0, $src1, $src2)
>;
multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> { multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
def : Pat < def : Pat <
(vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)),
(BFM $a, $b) (BFM $a, $b)
>; >;
def : Pat < def : Pat <
(vt (add (vt (shl 1, vt:$a)), -1)), (vt (add (vt (shl 1, vt:$a)), -1)),
▲ Show 20 Lines • Show All 70 Lines • Show Last 20 Lines

lib/Target/AMDGPU/VOP3Instructions.td

Show First 20 Lines • Show All 226 Lines • ▼ Show 20 Lines
def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>; def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>; def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
} // End isCommutable = 1 } // End isCommutable = 1
} // End SubtargetPredicate = isVI } // End SubtargetPredicate = isVI
def : Pat <
(i16 (select i1:$src0, i16:$src1, i16:$src2)),
(V_CNDMASK_B32_e64 $src2, $src1, $src0)
>;
let Predicates = [isVI] in { let Predicates = [isVI] in {
multiclass Tenary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2, multiclass Tenary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
Instruction inst, SDPatternOperator op3> { Instruction inst, SDPatternOperator op3> {
def : Pat< def : Pat<
(op2 (op1 i16:$src0, i16:$src1), i16:$src2), (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
(inst i16:$src0, i16:$src1, i16:$src2) (inst i16:$src0, i16:$src1, i16:$src2)
>; >;
▲ Show 20 Lines • Show All 205 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/select.f16.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}select_f16
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define void @select_f16(
half addrspace(1)* %r,
half addrspace(1)* %a,
half addrspace(1)* %b,
half addrspace(1)* %c,
half addrspace(1)* %d) {
entry:
%a.val = load half, half addrspace(1)* %a
%b.val = load half, half addrspace(1)* %b
%c.val = load half, half addrspace(1)* %c
%d.val = load half, half addrspace(1)* %d
%fcmp = fcmp olt half %a.val, %b.val
%r.val = select i1 %fcmp, half %c.val, half %d.val
store half %r.val, half addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_f16_imm_a
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], 0x3800{{$}}
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI: v_cmp_gt_f32_e32 vcc, v[[B_F32]], v[[A_F32]]
; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
; VI: v_mov_b32_e32 v[[A_F16:[0-9]+]], 0x3800{{$}}
; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define void @select_f16_imm_a(
half addrspace(1)* %r,
half addrspace(1)* %b,
half addrspace(1)* %c,
half addrspace(1)* %d) {
entry:
%b.val = load half, half addrspace(1)* %b
%c.val = load half, half addrspace(1)* %c
%d.val = load half, half addrspace(1)* %d
%fcmp = fcmp olt half 0xH3800, %b.val
%r.val = select i1 %fcmp, half %c.val, half %d.val
store half %r.val, half addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_f16_imm_b
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], 0x3800{{$}}
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
; VI: v_mov_b32_e32 v[[B_F16:[0-9]+]], 0x3800{{$}}
; VI: v_cmp_gt_f16_e32 vcc, v[[B_F16]], v[[A_F16]]
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define void @select_f16_imm_b(
half addrspace(1)* %r,
half addrspace(1)* %a,
half addrspace(1)* %c,
half addrspace(1)* %d) {
entry:
%a.val = load half, half addrspace(1)* %a
%c.val = load half, half addrspace(1)* %c
%d.val = load half, half addrspace(1)* %d
%fcmp = fcmp olt half %a.val, 0xH3800
%r.val = select i1 %fcmp, half %c.val, half %d.val
store half %r.val, half addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_f16_imm_c
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[D_F16:[0-9]+]]
; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], 0x3800{{$}}
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], v[[D_F16]]
; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
; VI: v_mov_b32_e32 v[[C_F16:[0-9]+]], 0x3800{{$}}
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define void @select_f16_imm_c(
half addrspace(1)* %r,
half addrspace(1)* %a,
half addrspace(1)* %b,
half addrspace(1)* %d) {
entry:
%a.val = load half, half addrspace(1)* %a
%b.val = load half, half addrspace(1)* %b
%d.val = load half, half addrspace(1)* %d
%fcmp = fcmp olt half %a.val, %b.val
%r.val = select i1 %fcmp, half 0xH3800, half %d.val
store half %r.val, half addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_f16_imm_d
; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[B_F16:[0-9]+]]
; GCN: buffer_load_ushort v[[C_F16:[0-9]+]]
; SI: v_cvt_f32_f16_e32 v[[D_F32:[0-9]+]], 0x3800{{$}}
; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
; SI: v_cvt_f32_f16_e32 v[[B_F32:[0-9]+]], v[[B_F16]]
; SI: v_cvt_f32_f16_e32 v[[C_F32:[0-9]+]], v[[C_F16]]
; SI: v_cmp_lt_f32_e32 vcc, v[[A_F32]], v[[B_F32]]
; SI: v_cndmask_b32_e32 v[[R_F32:[0-9]+]], v[[D_F32]], v[[C_F32]]
; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
; VI: v_cmp_lt_f16_e32 vcc, v[[A_F16]], v[[B_F16]]
; VI: v_mov_b32_e32 v[[D_F16:[0-9]+]], 0x3800{{$}}
; VI: v_cndmask_b32_e32 v[[R_F16:[0-9]+]], v[[D_F16]], v[[C_F16]], vcc
; GCN: buffer_store_short v[[R_F16]]
; GCN: s_endpgm
define void @select_f16_imm_d(
half addrspace(1)* %r,
half addrspace(1)* %a,
half addrspace(1)* %b,
half addrspace(1)* %c) {
entry:
%a.val = load half, half addrspace(1)* %a
%b.val = load half, half addrspace(1)* %b
%c.val = load half, half addrspace(1)* %c
%fcmp = fcmp olt half %a.val, %b.val
%r.val = select i1 %fcmp, half %c.val, half 0xH3800
store half %r.val, half addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_v2f16
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_lt_f32_e64
; SI: v_cmp_lt_f32_e32
; VI: v_cmp_lt_f16_e32
; VI: v_cmp_lt_f16_e64
; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e64
; SI: v_cvt_f16_f32_e32
; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm
define void @select_v2f16(
<2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %c,
<2 x half> addrspace(1)* %d) {
entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
%fcmp = fcmp olt <2 x half> %a.val, %b.val
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_v2f16_imm_a
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_gt_f32_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_gt_f32_e64
; VI: v_cmp_lt_f16_e32
; VI: v_cmp_lt_f16_e64
; GCN: v_cndmask_b32_e32
; SI: v_cvt_f16_f32_e32
; GCN: v_cndmask_b32_e64
; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm
define void @select_v2f16_imm_a(
<2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %c,
<2 x half> addrspace(1)* %d) {
entry:
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
%fcmp = fcmp olt <2 x half> <half 0xH3800, half 0xH3900>, %b.val
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_v2f16_imm_b
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_lt_f32_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_lt_f32_e64
; VI: v_cmp_gt_f16_e32
; VI: v_cmp_gt_f16_e64
; GCN: v_cndmask_b32_e32
; SI: v_cvt_f16_f32_e32
; GCN: v_cndmask_b32_e64
; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm
define void @select_v2f16_imm_b(
<2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %c,
<2 x half> addrspace(1)* %d) {
entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
%fcmp = fcmp olt <2 x half> %a.val, <half 0xH3800, half 0xH3900>
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> %d.val
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_v2f16_imm_c
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_lt_f32_e32
; SI: v_cmp_lt_f32_e64
; VI: v_cmp_lt_f16_e32
; VI: v_cmp_lt_f16_e64
; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e64
; SI: v_cvt_f16_f32_e32
; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm
define void @select_v2f16_imm_c(
<2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %d) {
entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%d.val = load <2 x half>, <2 x half> addrspace(1)* %d
%fcmp = fcmp olt <2 x half> %a.val, %b.val
%r.val = select <2 x i1> %fcmp, <2 x half> <half 0xH3800, half 0xH3900>, <2 x half> %d.val
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void
}
; GCN-LABEL: {{^}}select_v2f16_imm_d
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cvt_f32_f16_e32
; SI: v_cmp_lt_f32_e32
; SI: v_cmp_lt_f32_e64
; VI: v_cmp_lt_f16_e32
; VI: v_cmp_lt_f16_e64
; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e64
; SI: v_cvt_f16_f32_e32
; SI: v_cvt_f16_f32_e32
; GCN: s_endpgm
define void @select_v2f16_imm_d(
<2 x half> addrspace(1)* %r,
<2 x half> addrspace(1)* %a,
<2 x half> addrspace(1)* %b,
<2 x half> addrspace(1)* %c) {
entry:
%a.val = load <2 x half>, <2 x half> addrspace(1)* %a
%b.val = load <2 x half>, <2 x half> addrspace(1)* %b
%c.val = load <2 x half>, <2 x half> addrspace(1)* %c
%fcmp = fcmp olt <2 x half> %a.val, %b.val
%r.val = select <2 x i1> %fcmp, <2 x half> %c.val, <2 x half> <half 0xH3800, half 0xH3900>
store <2 x half> %r.val, <2 x half> addrspace(1)* %r
ret void
}