Uses function-relative jump table encodings on PowerPC64

[joerg]

Summary

Currently, the 64bit PowerPC port defaults to the generic jump table handling, which is not PIC. This patch implements the minimal platform specific version of D26018 for PPC64. Jump tables are encoded as GlobalBaseReg-relative 32bit offsets. This should work well both or large code models as well, assuming individual functions are still within 4GB.

The downside is that the current implementation requires the global base setup (two instructions) and one instruction more for the jump table branch. The former can likely be improved using a TOC-based pointer load, but that's outside the scope of this patch.

From a discussion on IRC, the TOC is not guaranteed to stay as continuous chunk, otherwise the jump table could directly be lowered unto the TOC at the cost of a larger table but without the instruction overhead.

[joerg]

Simplify the jump table handling. For PPC64, always use relative jump tables with the new hook from r286951. For the default, small and medium code model, use the existing difference from the jump table towards the label. For all other code models, setup the picbase and use the difference between the picbase and the block address.

Overall, this results in smaller data tables at the expensive of one more arithmetic operation. Given that we only create jump tables for more than two entries, it is a net win in size. For large code model, the only remaining assumption is that individual functions are no larger than 2GB.

[hfinkel]

Please post patches with full context.

lib/Target/PowerPC/PPCISelLowering.cpp

2190

Please add a comment here explaining why we always use relative jump tables, even in non-PIC mode.

2194

No need for this blank line.

2199

The logic here seems unnecessarily complex. Please just do:

if (!Subtarget.isPPC64() || getTargetMachine().getCodeModel() != CodeModel::Large)
  return TargetLowering::getPICJumpTableRelocBase(Table, DAG);

return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
                     getPointerTy(DAG.getDataLayout()));

2212

Please separate the function definitions with a blank line.

2216

Regarding logic complexity, please refactor as for the function above.

[joerg]

Add comment on why the relative encoding is always useful on PPC64. Fix formatting.

[joerg]

lib/Target/PowerPC/PPCISelLowering.cpp

2199

I disagree. The reason for keeping the branches separate is to make it easier to see that PPC32 always gets the default behavior.

It is not just the large code model that has to be handled carefully here, but also JIT. I don't even know what guarantees the (potential) kernel code model would provide.

2216

Same as above.

[hfinkel]

LGTM

lib/Target/PowerPC/PPCISelLowering.cpp

2184

Bit -> bits

Add a period after instructions.

2199

Okay.

[joerg]

lib/Target/PowerPC/PPCISelLowering.cpp

2184

First done, second not. The sentence is not done at that point. I'm not sure if we actually ever create multiple jumps via the same jump table, but let's not rule that part out complete :)

lib/Target/PowerPC/PPCISelLowering.h

public:
     unsigned
     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 
     /// Override to support customized stack guard loading.
     bool useLoadStackGuardNode() const override;
     void insertSSPDeclarations(Module &M) const override;
 
     bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
+
+    unsigned getJumpTableEncoding() const override;
+    bool isJumpTableRelative() const override;
+    SDValue getPICJumpTableRelocBase(SDValue Table,
+                                     SelectionDAG &DAG) const override;
+    const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
+                                               unsigned JTI,
+                                               MCContext &Ctx) const override;
+
   private:
     struct ReuseLoadInfo {
       SDValue Ptr;
       SDValue Chain;
       SDValue ResChain;
       MachinePointerInfo MPI;
       bool IsDereferenceable;
       bool IsInvariant;

lib/Target/PowerPC/PPCISelLowering.cpp

 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineJumpTableInfo.h"
 #include "llvm/CodeGen/MachineLoopInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/Constants.h"
 #include "llvm/IR/DerivedTypes.h"
 #include "llvm/IR/Function.h"

 
   SDValue CPIHi =
     DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
   SDValue CPILo =
     DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
   return LowerLabelRef(CPIHi, CPILo, IsPIC, DAG);
 }
 
+// For 64-bit PowerPC, prefer the more compact relative encodings.
+// This trades 32 Bit per jump table entry for one or two instructions
+// on the jump site.
+unsigned PPCTargetLowering::getJumpTableEncoding() const {
+  if (isJumpTableRelative())
+    return MachineJumpTableInfo::EK_LabelDifference32;
+
+  return TargetLowering::getJumpTableEncoding();
+}
+
+bool PPCTargetLowering::isJumpTableRelative() const {
+  if (Subtarget.isPPC64())
+    return true;
+  return TargetLowering::isJumpTableRelative();
+}
+
+SDValue PPCTargetLowering::getPICJumpTableRelocBase(SDValue Table,
+                                                    SelectionDAG &DAG) const {
+  if (!Subtarget.isPPC64())
+    return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
+
+  switch (getTargetMachine().getCodeModel()) {
+  case CodeModel::Default:
+  case CodeModel::Small:
+  case CodeModel::Medium:
+    return TargetLowering::getPICJumpTableRelocBase(Table, DAG);
+  default:
+    return DAG.getNode(PPCISD::GlobalBaseReg, SDLoc(),
+                       getPointerTy(DAG.getDataLayout()));
+  }
+}
+
+const MCExpr *
+PPCTargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
+                                                unsigned JTI,
+                                                MCContext &Ctx) const {
+  if (!Subtarget.isPPC64())
+    return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
+
+  switch (getTargetMachine().getCodeModel()) {
+  case CodeModel::Default:
+  case CodeModel::Small:
+  case CodeModel::Medium:
+    return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx);
+  default:
+    return MCSymbolRefExpr::create(MF->getPICBaseSymbol(), Ctx);
+  }
+}
+
 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
   EVT PtrVT = Op.getValueType();
   JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
 
   // 64-bit SVR4 ABI code is always position-independent.
   // The actual address of the GlobalValue is stored in the TOC.
   if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
     setUsesTOCBasePtr(DAG);

test/CodeGen/PowerPC/mcm-5.ll

 ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -code-model=medium <%s | FileCheck %s
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -code-model=large <%s | FileCheck %s
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -code-model=large <%s | FileCheck -check-prefix=LARGE  %s
 
 ; Test correct code generation for medium and large code model
 ; for loading the address of a jump table from the TOC.
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 
 define signext i32 @test_jump_table(i32 signext %i) nounwind {
sw.bb3:                                           ; preds = %entry, %sw.bb2
   %shl = shl i32 %4, 1
   store i32 %shl, i32* %i.addr, align 4
   br label %sw.epilog
 
 sw.epilog:                                        ; preds = %sw.bb3, %sw.default
   %5 = load i32, i32* %i.addr, align 4
   ret i32 %5
 }
-
 ; CHECK-LABEL: test_jump_table:
-; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
-; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
-; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
-; CHECK: .section .toc
-; CHECK: .LC[[TOCNUM]]:
-; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}
+; CHECK-NOT:       bl .L0$pb
+
+; CHECK:       addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
+; CHECK:       ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
+; CHECK:       lwax [[REG3:[0-9]+]], {{[0-9]+}}, [[REG2]]
+; CHECK-NEXT:  add  [[REG4:[0-9]+]], [[REG3]], [[REG2]]
+; CHECK-NEXT:  mtctr [[REG4]]
+; CHECK-NEXT:  bctr
+
+; CHECK-LABEL: .LJTI0_0:
+; CHECK-NEXT: .long .LBB0_{{[0-9]+}}-.LJTI0_0
+
+; LARGE-LABEL: test_jump_table:
+; LARGE:       bl .L0$pb
+; LARGE-NEXT:  .L0$pb:
+; LARGE:       mflr [[REGBASE:[0-9]+]]
+
+; LARGE:       addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
+; LARGE:       ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
+; LARGE:       lwax [[REG3:[0-9]+]], {{[0-9]+}}, [[REG2]]
+; LARGE-NEXT:  add  [[REG4:[0-9]+]], [[REG3]], [[REGBASE]]
+; LARGE-NEXT:  mtctr [[REG4]]
+; LARGE-NEXT:  bctr
+
+; LARGE-LABEL: .LJTI0_0:
+; LARGE-NEXT: .long .LBB0_{{[0-9]+}}-.L0$pb