[Power9] vector load/store with length - llvm portion

[syzaara]

Summary

Add builtin functions for prototypes:

vector signed char vec_xl_len (signed char *, size_t);
vector unsigned char vec_xl_len (unsigned char *, size_t);
vector signed int vec_xl_len (signed int *, size_t);
vector unsigned int vec_xl_len (unsigned int *, size_t);
vector signed int128 vec_xl_len (signed int128 *, size_t);
vector unsigned int128 vec_xl_len (unsigned int128 *, size_t);
vector signed long long vec_xl_len (signed long long *, size_t);
vector unsigned long long vec_xl_len (unsigned long long *, size_t);
vector signed short vec_xl_len (signed short *, size_t);
vector unsigned short vec_xl_len (unsigned short *, size_t);
vector double vec_xl_len (double *, size_t);
vector float vec_xl_len (float *, size_t);

vector unsigned char vec_xl_len_r (unsigned char *, size_t);

void vec_xst_len (vector signed char, signed char *, size_t);
void vec_xst_len (vector unsigned char, unsigned char *, size_t);
void vec_xst_len (vector signed int, signed int *, size_t);
void vec_xst_len (vector unsigned int, unsigned int *, size_t);
void vec_xst_len (vector signed int128, signed int128 *, size_t);
void vec_xst_len (vector unsigned int128, unsigned int128 *, size_t);
void vec_xst_len (vector signed long long, signed long long *, size_t);
void vec_xst_len (vector unsigned long long, unsigned long long *, size_t);
void vec_xst_len (vector signed short, signed short *, size_t);
void vec_xst_len (vector unsigned short, unsigned short *, size_t);
void vec_xst_len (vector double, double *, size_t);
void vec_xst_len (vector float, float *, size_t);

void vec_xst_len_r (vector unsigned char, unsigned char *, size_t);

[kbarton]

LGTM

[nemanjai]

include/llvm/IR/IntrinsicsPowerPC.td

724

I realized after we spoke yesterday that we have to change this. The length operand is in bits 0-7 of the second GPR operand. It therefore means that we cannot model this with an i32 so the instructions operands need to be G8RC and this has to be llvm_i64_ty.

lib/Target/PowerPC/PPCInstrVSX.td

2298–2305

See comment above.

[syzaara]

Updates for length parameter to be 64 bits rather than 32 bits.

[nemanjai]

Other than the few minor nits about indentation, this LGTM.

include/llvm/IR/IntrinsicsPowerPC.td

724

Please fix the indentation as follows:

def int_ppc_vsx_lxvl :
      Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty],
                [IntrReadMem, IntrArgMemOnly]>;

Same comment for the definitions below. The third line has the entire contents of the list enclosed in [] and it lines up inside the angle bracket since it is an argument to the Intrinsic.

lib/Target/PowerPC/PPCInstrVSX.td

2299

Same as above, the double quote character lines up under the 3 on the line above.

2301

This should line up with the XX1Form above since it is another class that this definition inherits from.

2349

Same indentation comment as above.

include/llvm/IR/IntrinsicsPowerPC.td

 
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
 
 // Vector load.
 def int_ppc_vsx_lxvw4x :
       Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
 def int_ppc_vsx_lxvd2x :
       Intrinsic<[llvm_v2f64_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
+def int_ppc_vsx_lxvl :
+      Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem,
+      IntrArgMemOnly]>;
+def int_ppc_vsx_lxvll :
+      Intrinsic<[llvm_v4i32_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrReadMem,
+      IntrArgMemOnly]>;
+def int_ppc_vsx_stxvl :
+      Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
+      [IntrArgMemOnly]>;
+def int_ppc_vsx_stxvll :
+      Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty, llvm_i64_ty],
+      [IntrArgMemOnly]>;
 
 // Vector store.
 def int_ppc_vsx_stxvw4x :
       Intrinsic<[], [llvm_v4i32_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
 def int_ppc_vsx_stxvd2x :
       Intrinsic<[], [llvm_v2f64_ty, llvm_ptr_ty], [IntrArgMemOnly]>;
 
 // Vector and scalar maximum.

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   def LXVH8X  : X_XT6_RA5_RB5<31, 812, "lxvh8x" , vsrc, []>;
   def LXVB16X : X_XT6_RA5_RB5<31, 876, "lxvb16x", vsrc, []>;
 
   // Load Vector Indexed
   def LXVX    : X_XT6_RA5_RB5<31, 268, "lxvx"   , vsrc,
                 [(set v2f64:$XT, (load xoaddr:$src))]>;
 
   // Load Vector (Left-justified) with Length
-  def LXVL    : X_XT6_RA5_RB5<31, 269, "lxvl"   , vsrc, []>;
-  def LXVLL   : X_XT6_RA5_RB5<31, 301, "lxvll"  , vsrc, []>;
+  def LXVL : XX1Form<31, 269, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
+                   "lxvl $XT, $src, $rB", IIC_LdStLoad,
+                   [(set v4i32:$XT, (int_ppc_vsx_lxvl addr:$src, i64:$rB))]>,
+                    UseVSXReg;
+  def LXVLL : XX1Form<31,301, (outs vsrc:$XT), (ins memr:$src, g8rc:$rB),
+                   "lxvll $XT, $src, $rB", IIC_LdStLoad,
+                   [(set v4i32:$XT, (int_ppc_vsx_lxvll addr:$src, i64:$rB))]>,
+                    UseVSXReg;
 
   // Load Vector Word & Splat Indexed
   def LXVWSX  : X_XT6_RA5_RB5<31, 364, "lxvwsx" , vsrc, []>;
   } // mayLoad
 
   // When adding new D-Form loads/stores, be sure to update the ImmToIdxMap in
   // PPCRegisterInfo::PPCRegisterInfo and maybe save yourself some debugging.
   let mayStore = 1 in {
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   def STXVH8X  : X_XS6_RA5_RB5<31,  940, "stxvh8x" , vsrc, []>;
   def STXVB16X : X_XS6_RA5_RB5<31, 1004, "stxvb16x", vsrc, []>;
 
   // Store Vector Indexed
   def STXVX    : X_XS6_RA5_RB5<31,  396, "stxvx"   , vsrc,
                  [(store v2f64:$XT, xoaddr:$dst)]>;
 
   // Store Vector (Left-justified) with Length
-  def STXVL    : X_XS6_RA5_RB5<31,  397, "stxvl"   , vsrc, []>;
-  def STXVLL   : X_XS6_RA5_RB5<31,  429, "stxvll"  , vsrc, []>;
+  def STXVL : XX1Form<31, 397, (outs), (ins vsrc:$XT, memr:$dst, g8rc:$rB),
+                   "stxvl $XT, $dst, $rB", IIC_LdStLoad,
+                   [(int_ppc_vsx_stxvl v4i32:$XT, addr:$dst, i64:$rB)]>,
+                    UseVSXReg;
+  def STXVLL : XX1Form<31, 429, (outs), (ins vsrc:$XT, memr:$dst, g8rc:$rB),
+                   "stxvll $XT, $dst, $rB", IIC_LdStLoad,
+                   [(int_ppc_vsx_stxvll v4i32:$XT, addr:$dst, i64:$rB)]>,
+                    UseVSXReg;
   } // mayStore
 
   // Patterns for which instructions from ISA 3.0 are a better match
   let Predicates = [IsLittleEndian, HasP9Vector] in {
   def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 0))))),
             (f32 (XSCVUXDSP (XXEXTRACTUW $A, 12)))>;
   def : Pat<(f32 (PPCfcfidus (PPCmtvsrz (i32 (extractelt v4i32:$A, 1))))),
             (f32 (XSCVUXDSP (XXEXTRACTUW $A, 8)))>;

test/CodeGen/PowerPC/vsx-p9.ll

entry:
   ret <16 x i8> %0
 ; CHECK-LABEL: testVSRV
 ; CHECK: vsrv 2, 2, 3
 ; CHECK: blr
 }
 ; Function Attrs: nounwind readnone
 declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>)
 
+; Function Attrs: nounwind readnone
+define <4 x i32> @testLXVL(i8* %a, i64 %b) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvl(i8* %a, i64 %b)
+  ret <4 x i32> %0
+; CHECK-LABEL: testLXVL
+; CHECK: lxvl 34, 3, 4
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.lxvl(i8*, i64)
+
+define void @testSTXVL(<4 x i32> %a, i8* %b, i64 %c) {
+entry:
+  tail call void @llvm.ppc.vsx.stxvl(<4 x i32> %a, i8* %b, i64 %c)
+  ret void
+; CHECK-LABEL: testSTXVL
+; CHECK: stxvl 34, 5, 6
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare void @llvm.ppc.vsx.stxvl(<4 x i32>, i8*, i64)
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @testLXVLL(i8* %a, i64 %b) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.vsx.lxvll(i8* %a, i64 %b)
+  ret <4 x i32> %0
+; CHECK-LABEL: testLXVLL
+; CHECK: lxvll 34, 3, 4
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.vsx.lxvll(i8*, i64)
+
+define void @testSTXVLL(<4 x i32> %a, i8* %b, i64 %c) {
+entry:
+  tail call void @llvm.ppc.vsx.stxvll(<4 x i32> %a, i8* %b, i64 %c)
+  ret void
+; CHECK-LABEL: testSTXVLL
+; CHECK: stxvll 34, 5, 6
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare void @llvm.ppc.vsx.stxvll(<4 x i32>, i8*, i64)
+
 declare void @sink(...)