[AMDGPU] Expand vector mulhu/mulhs

[vpykhtin]

Summary

fix for SWDEV-103793.

[nhaustov]

Can you also add test on mulhs?

[arsenm]

test/CodeGen/AMDGPU/scalarize-ops.ll

1–2 ↗

(On Diff #76195)

This test looks like it should be moved into udiv.ll. Is there a simpler way to expose mulhs usage?

[vpykhtin]

test/CodeGen/AMDGPU/scalarize-ops.ll

1–2 ↗

(On Diff #76195)

I'll try to find out, along with test on mulhs.

[vpykhtin]

added mulhs test and moved it to udiv.ll and sdiv.ll

It looks like div is the most stable way to expose mulhs/mulhu.

[arsenm]

LGTM

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
 
   for (MVT VT : VectorIntTypes) {
     // Expand the following operations for the current type by default.
     setOperationAction(ISD::ADD,  VT, Expand);
     setOperationAction(ISD::AND,  VT, Expand);
     setOperationAction(ISD::FP_TO_SINT, VT, Expand);
     setOperationAction(ISD::FP_TO_UINT, VT, Expand);
     setOperationAction(ISD::MUL,  VT, Expand);
+    setOperationAction(ISD::MULHU, VT, Expand);
+    setOperationAction(ISD::MULHS, VT, Expand);
     setOperationAction(ISD::OR,   VT, Expand);
     setOperationAction(ISD::SHL,  VT, Expand);
     setOperationAction(ISD::SRA,  VT, Expand);
     setOperationAction(ISD::SRL,  VT, Expand);
     setOperationAction(ISD::ROTL, VT, Expand);
     setOperationAction(ISD::ROTR, VT, Expand);
     setOperationAction(ISD::SUB,  VT, Expand);
     setOperationAction(ISD::SINT_TO_FP, VT, Expand);

test/CodeGen/AMDGPU/sdiv.ll

 
 ; define void @test_get_quotient_and_remainder(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
 ;   %resultdiv = sdiv i64 %a, %b
 ;   %resultrem = srem i64 %a, %b
 ;   %result = add i64 %resultdiv, %resultrem
 ;   store i64 %result, i64 addrspace(1)* %out, align 8
 ;   ret void
 ; }
+
+; FUNC-LABEL: @scalarize_mulhs_4xi32
+; SI: v_mul_hi_i32
+; SI: v_mul_hi_i32
+; SI: v_mul_hi_i32
+; SI: v_mul_hi_i32
+
+define void @scalarize_mulhs_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
+  %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
+  %2 = sdiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
+  store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
+  ret void
+}

test/CodeGen/AMDGPU/udiv.ll

define void @v_udiv_i24(i32 addrspace(1)* %out, i24 addrspace(1)* %in) {
   %den_ptr = getelementptr i24, i24 addrspace(1)* %in, i24 1
   %num = load i24, i24 addrspace(1) * %in
   %den = load i24, i24 addrspace(1) * %den_ptr
   %result = udiv i24 %num, %den
   %result.ext = zext i24 %result to i32
   store i32 %result.ext, i32 addrspace(1)* %out
   ret void
 }
+
+; FUNC-LABEL: @scalarize_mulhu_4xi32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+; SI: v_mul_hi_u32
+
+define void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
+  %1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
+  %2 = udiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
+  store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
+  ret void
+}
+