This is an archive of the discontinued LLVM Phabricator instance.

[AMDGPU] Expand vector mulhu/mulhs
ClosedPublic

Authored by vpykhtin on Oct 28 2016, 8:29 AM.

Download Raw Diff

Details

Reviewers

• tstellarAMD
arsenm

Commits

rG8a89d3662a8c: [AMDGPU] Expand vector mulhu/mulhs
rL285684: [AMDGPU] Expand vector mulhu/mulhs

Summary

fix for SWDEV-103793.

Diff Detail

Build Status

Buildable 866
Build 866: arc lint + arc unit

Event Timeline

vpykhtin updated this revision to Diff 76195.Oct 28 2016, 8:29 AM

vpykhtin retitled this revision from to [AMDGPU] Expand vector mulhu/mulhs .

vpykhtin updated this object.

vpykhtin added reviewers: arsenm, • tstellarAMD.

vpykhtin set the repository for this revision to rL LLVM.

vpykhtin added a subscriber: nhaustov.

Herald edited edge metadata. · View Herald TranscriptOct 28 2016, 8:29 AM

Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald Transcript

Can you also add test on mulhs?

arsenm added inline comments.Oct 28 2016, 11:19 AM

test/CodeGen/AMDGPU/scalarize-ops.ll
1–2	This test looks like it should be moved into udiv.ll. Is there a simpler way to expose mulhs usage?

vpykhtin added inline comments.Oct 28 2016, 11:32 AM

test/CodeGen/AMDGPU/scalarize-ops.ll
1–2	I'll try to find out, along with test on mulhs.

added mulhs test and moved it to udiv.ll and sdiv.ll

It looks like div is the most stable way to expose mulhs/mulhu.

Herald edited edge metadata. · View Herald TranscriptOct 31 2016, 9:16 AM

LGTM

This revision is now accepted and ready to land.Oct 31 2016, 5:28 PM

Closed by commit rL285684: [AMDGPU] Expand vector mulhu/mulhs (authored by vpykhtin). · Explain WhyNov 1 2016, 3:37 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

lib/

Target/

AMDGPU/

AMDGPUISelLowering.cpp

2 lines

test/

CodeGen/

AMDGPU/

scalarize-ops.ll

15 lines

Diff 76195

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 353 Lines • ▼ Show 20 Lines	AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,

for (MVT VT : VectorIntTypes) {		for (MVT VT : VectorIntTypes) {
// Expand the following operations for the current type by default.		// Expand the following operations for the current type by default.
setOperationAction(ISD::ADD, VT, Expand);		setOperationAction(ISD::ADD, VT, Expand);
setOperationAction(ISD::AND, VT, Expand);		setOperationAction(ISD::AND, VT, Expand);
setOperationAction(ISD::FP_TO_SINT, VT, Expand);		setOperationAction(ISD::FP_TO_SINT, VT, Expand);
setOperationAction(ISD::FP_TO_UINT, VT, Expand);		setOperationAction(ISD::FP_TO_UINT, VT, Expand);
setOperationAction(ISD::MUL, VT, Expand);		setOperationAction(ISD::MUL, VT, Expand);
		setOperationAction(ISD::MULHU, VT, Expand);
		setOperationAction(ISD::MULHS, VT, Expand);
setOperationAction(ISD::OR, VT, Expand);		setOperationAction(ISD::OR, VT, Expand);
setOperationAction(ISD::SHL, VT, Expand);		setOperationAction(ISD::SHL, VT, Expand);
setOperationAction(ISD::SRA, VT, Expand);		setOperationAction(ISD::SRA, VT, Expand);
setOperationAction(ISD::SRL, VT, Expand);		setOperationAction(ISD::SRL, VT, Expand);
setOperationAction(ISD::ROTL, VT, Expand);		setOperationAction(ISD::ROTL, VT, Expand);
setOperationAction(ISD::ROTR, VT, Expand);		setOperationAction(ISD::ROTR, VT, Expand);
setOperationAction(ISD::SUB, VT, Expand);		setOperationAction(ISD::SUB, VT, Expand);
setOperationAction(ISD::SINT_TO_FP, VT, Expand);		setOperationAction(ISD::SINT_TO_FP, VT, Expand);
▲ Show 20 Lines • Show All 2,601 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/scalarize-ops.ll

This file was added.

				; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s
				; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s
				arsenmUnsubmitted Not Done Reply Inline Actions This test looks like it should be moved into udiv.ll. Is there a simpler way to expose mulhs usage? arsenm: This test looks like it should be moved into udiv.ll. Is there a simpler way to expose mulhs…
				vpykhtinAuthorUnsubmitted Not Done Reply Inline Actions I'll try to find out, along with test on mulhs. vpykhtin: I'll try to find out, along with test on mulhs.

				; GCN-LABEL: @scalarize_mulhu_4xi32
				; GCN: v_mul_hi_u32
				; GCN: v_mul_hi_u32
				; GCN: v_mul_hi_u32
				; GCN: v_mul_hi_u32

				define void @scalarize_mulhu_4xi32(<4 x i32> addrspace(1)* nocapture readonly %in, <4 x i32> addrspace(1)* nocapture %out) {
				%1 = load <4 x i32>, <4 x i32> addrspace(1)* %in, align 16
				%2 = udiv <4 x i32> %1, <i32 53668, i32 53668, i32 53668, i32 53668>
				store <4 x i32> %2, <4 x i32> addrspace(1)* %out, align 16
				ret void
				}