Implement vector count leading/trailing bytes with zero lsb and vector parity builtins - llvm portion

[syzaara]

Summary

Implement builtins for prototypes:

signed int vec_cntlz_lsbb (vector signed char);
signed int vec_cntlz_lsbb (vector unsigned char);
signed int vec_cnttz_lsbb (vector signed char);
signed int vec_cnttz_lsbb (vector unsigned char);
vector unsigned int vec_parity_lsbb (vector signed int);
vector unsigned int vec_parity_lsbb (vector unsigned int);
vector unsigned int128 vec_parity_lsbb (vector signed int128);
vector unsigned int128 vec_parity_lsbb (vector unsigned int128);
vector unsigned long long vec_parity_lsbb (vector signed long long);
vector unsigned long long vec_parity_lsbb (vector unsigned long long);

[nemanjai]

Other than the formatting, this LGTM.

lib/Target/PowerPC/PPCInstrAltivec.td

1285

Please keep the indentation consistent - the first character of the second line lines up with the first operand in the angle bracket.

1286

also, the spacing is weird here, please keep it consistent:
(set i32:$rD, (int_....

[kbarton]

LGTM

[syzaara]

Fix formatting.

[nemanjai]

Committed revision 285434.
Zaara, please close this review if there are no buildbot failures.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vcmpgtub_p : GCCBuiltin<"__builtin_altivec_vcmpgtub_p">,
               Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vcmpneb_p : GCCBuiltin<"__builtin_altivec_vcmpneb_p">,
               Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vcmpnezb_p : GCCBuiltin<"__builtin_altivec_vcmpnezb_p">,
               Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v16i8_ty,llvm_v16i8_ty],
                         [IntrNoMem]>;
+  def int_ppc_altivec_vclzlsbb : GCCBuiltin<"__builtin_altivec_vclzlsbb">,
+              Intrinsic<[llvm_i32_ty],[llvm_v16i8_ty],[IntrNoMem]>;
+  def int_ppc_altivec_vctzlsbb : GCCBuiltin<"__builtin_altivec_vctzlsbb">,
+              Intrinsic<[llvm_i32_ty],[llvm_v16i8_ty],[IntrNoMem]>;
+  def int_ppc_altivec_vprtybw : GCCBuiltin<"__builtin_altivec_vprtybw">,
+              Intrinsic<[llvm_v4i32_ty],[llvm_v4i32_ty],[IntrNoMem]>;
+  def int_ppc_altivec_vprtybd : GCCBuiltin<"__builtin_altivec_vprtybd">,
+              Intrinsic<[llvm_v2i64_ty],[llvm_v2i64_ty],[IntrNoMem]>;
+  def int_ppc_altivec_vprtybq : GCCBuiltin<"__builtin_altivec_vprtybq">,
+              Intrinsic<[llvm_v1i128_ty],[llvm_v1i128_ty],[IntrNoMem]>;
+
 }
 
 // Vector average.
 def int_ppc_altivec_vavgsb : PowerPC_Vec_BBB_Intrinsic<"vavgsb">;
 def int_ppc_altivec_vavgsh : PowerPC_Vec_HHH_Intrinsic<"vavgsh">;
 def int_ppc_altivec_vavgsw : PowerPC_Vec_WWW_Intrinsic<"vavgsw">;
 def int_ppc_altivec_vavgub : PowerPC_Vec_BBB_Intrinsic<"vavgub">;
 def int_ppc_altivec_vavguh : PowerPC_Vec_HHH_Intrinsic<"vavguh">;

lib/Target/PowerPC/PPCInstrAltivec.td

 class VX_VT5_EO5_VB5<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
   : VXForm_RD5_XO5_RS5<xo, eo, (outs vrrc:$vD), (ins vrrc:$vB),
                        !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
 class VX_VT5_EO5_VB5s<bits<11> xo, bits<5> eo, string opc, list<dag> pattern>
   : VXForm_RD5_XO5_RS5<xo, eo, (outs vfrc:$vD), (ins vfrc:$vB),
                        !strconcat(opc, " $vD, $vB"), IIC_VecGeneral, pattern>;
 
 // Vector Count Leading/Trailing Zero LSB. Result is placed into GPR[rD]
-def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs g8rc:$rD), (ins vrrc:$vB),
-                                  "vclzlsbb $rD, $vB", IIC_VecGeneral, []>;
-def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs g8rc:$rD), (ins vrrc:$vB),
-                                  "vctzlsbb $rD, $vB", IIC_VecGeneral, []>;
+def VCLZLSBB : VXForm_RD5_XO5_RS5<1538, 0, (outs gprc:$rD), (ins vrrc:$vB),
+                                  "vclzlsbb $rD, $vB", IIC_VecGeneral,
+                                  [(set i32:$rD, (int_ppc_altivec_vclzlsbb
+                                  v16i8:$vB))]>;
+def VCTZLSBB : VXForm_RD5_XO5_RS5<1538, 1, (outs gprc:$rD), (ins vrrc:$vB),
+                                  "vctzlsbb $rD, $vB", IIC_VecGeneral,
+                                  [(set i32:$rD, (int_ppc_altivec_vctzlsbb
+                                  v16i8:$vB))]>;
 // Vector Count Trailing Zeros
 def VCTZB : VX_VT5_EO5_VB5<1538, 28, "vctzb",
                            [(set v16i8:$vD, (cttz v16i8:$vB))]>;
 def VCTZH : VX_VT5_EO5_VB5<1538, 29, "vctzh",
                            [(set v8i16:$vD, (cttz v8i16:$vB))]>;
 def VCTZW : VX_VT5_EO5_VB5<1538, 30, "vctzw",
                            [(set v4i32:$vD, (cttz v4i32:$vB))]>;
 def VCTZD : VX_VT5_EO5_VB5<1538, 31, "vctzd",
let isCodeGenOnly = 1 in {
   def VEXTSW2Ds : VX_VT5_EO5_VB5s<1538, 26, "vextsw2d", []>;
 }
 
 // Vector Integer Negate
 def VNEGW : VX_VT5_EO5_VB5<1538, 6, "vnegw", []>;
 def VNEGD : VX_VT5_EO5_VB5<1538, 7, "vnegd", []>;
 
 // Vector Parity Byte
-def VPRTYBW : VX_VT5_EO5_VB5<1538,  8, "vprtybw", []>;
-def VPRTYBD : VX_VT5_EO5_VB5<1538,  9, "vprtybd", []>;
-def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", []>;
+def VPRTYBW : VX_VT5_EO5_VB5<1538, 8, "vprtybw", [(set v4i32:$vD,
+                            (int_ppc_altivec_vprtybw v4i32:$vB))]>;
+def VPRTYBD : VX_VT5_EO5_VB5<1538,  9, "vprtybd", [(set v2i64:$vD,
+                            (int_ppc_altivec_vprtybd v2i64:$vB))]>;
+def VPRTYBQ : VX_VT5_EO5_VB5<1538, 10, "vprtybq", [(set v1i128:$vD,
+                            (int_ppc_altivec_vprtybq v1i128:$vB))]>;
 
 // Vector (Bit) Permute (Right-indexed)
 def VBPERMD : VXForm_1<1484, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                        "vbpermd $vD, $vA, $vB", IIC_VecFP, []>;
 def VPERMR : VAForm_1a<59, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
                        "vpermr $vD, $vA, $vB, $vC", IIC_VecFP, []>;
 
 class VX1_VT5_VA5_VB5<bits<11> xo, string opc, list<dag> pattern>

test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll

 ; Function Attrs: nounwind readnone
 declare <8 x i16> @llvm.cttz.v8i16(<8 x i16>, i1)
 
 ; Function Attrs: nounwind readnone
 declare <4 x i32> @llvm.cttz.v4i32(<4 x i32>, i1)
 
 ; Function Attrs: nounwind readnone
 declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1)
+
+; Function Attrs: nounwind readnone
+define i32 @testVCLZLSBB(<16 x i8> %a) {
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8> %a)
+  ret i32 %0
+; CHECK-LABEL: testVCLZLSBB
+; CHECK: vclzlsbb 3, 2
+}
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.altivec.vclzlsbb(<16 x i8>)
+
+; Function Attrs: nounwind readnone
+define i32 @testVCTZLSBB(<16 x i8> %a) {
+entry:
+  %0 = tail call i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8> %a)
+  ret i32 %0
+; CHECK-LABEL: testVCTZLSBB
+; CHECK: vctzlsbb 3, 2
+}
+; Function Attrs: nounwind readnone
+declare i32 @llvm.ppc.altivec.vctzlsbb(<16 x i8>)
+
+; Function Attrs: nounwind readnone
+define <4 x i32> @testVPRTYBW(<4 x i32> %a) {
+entry:
+  %0 = tail call <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32> %a)
+  ret <4 x i32> %0
+; CHECK-LABEL: testVPRTYBW
+; CHECK: vprtybw 2, 2
+}
+; Function Attrs: nounwind readnone
+declare <4 x i32> @llvm.ppc.altivec.vprtybw(<4 x i32>)
+
+; Function Attrs: nounwind readnone
+define <2 x i64> @testVPRTYBD(<2 x i64> %a) {
+entry:
+  %0 = tail call <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64> %a)
+  ret <2 x i64> %0
+; CHECK-LABEL: testVPRTYBD
+; CHECK: vprtybd 2, 2
+}
+; Function Attrs: nounwind readnone
+declare <2 x i64> @llvm.ppc.altivec.vprtybd(<2 x i64>)
+
+; Function Attrs: nounwind readnone
+define <1 x i128> @testVPRTYBQ(<1 x i128> %a) {
+entry:
+  %0 = tail call <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128> %a)
+  ret <1 x i128> %0
+; CHECK-LABEL: testVPRTYBQ
+; CHECK: vprtybq 2, 2
+}
+; Function Attrs: nounwind readnone
+declare <1 x i128> @llvm.ppc.altivec.vprtybq(<1 x i128>)