Implement vec_insert_exp builtins - llvm portion

[syzaara]

Summary

Add vec_insert_exp with prototypes:

vector double vec_insert_exp (vector double, vector unsigned long long);
vector double vec_insert_exp (vector unsigned long long, vector unsigned long long);
vector float vec_insert_exp (vector float, vector unsigned int);
vector float vec_insert_exp (vector unsigned int, vector unsigned int);

[nemanjai]

Just a couple of minor inline comments, but a very nice patch otherwise. Thanks Zaara.

include/llvm/IR/IntrinsicsPowerPC.td

785

Just curious, why not inherit from PowerPC_VSX_Intrinsic?

test/CodeGen/PowerPC/vsx-p9.ll

164

All 3 of the operand registers are locked in by the ABI, so I think it is reasonable to completely specify this check pattern. The same applies for both tests. For example:
xviexpdp 34, 34, 35

[echristo]

LGTM when Nemanja is happy.

-eric

[syzaara]

Changed to inherit from PowerPC_VSX_Intrinsic and added register numbers to test.

[nemanjai]

Committed revision 285225.
Zaara, please close this revision when you get in if there are no failures.

include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_vsx_xvcmpgtsp :
       PowerPC_VSX_Intrinsic<"xvcmpgtsp", [llvm_v4i32_ty],
                             [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>;
 def int_ppc_vsx_xvcmpgtsp_p : GCCBuiltin<"__builtin_vsx_xvcmpgtsp_p">,
               Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_v4f32_ty,llvm_v4f32_ty],
                         [IntrNoMem]>;
 def int_ppc_vsx_xxleqv :
       PowerPC_VSX_Intrinsic<"xxleqv", [llvm_v4i32_ty],
                             [llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
+def int_ppc_vsx_xviexpdp :
+      PowerPC_VSX_Intrinsic<"xviexpdp",[llvm_v2f64_ty],
+                            [llvm_v2i64_ty, llvm_v2i64_ty],[IntrNoMem]>;
+def int_ppc_vsx_xviexpsp :
+      PowerPC_VSX_Intrinsic<"xviexpsp",[llvm_v4f32_ty],
+                            [llvm_v4i32_ty, llvm_v4i32_ty],[IntrNoMem]>;
 }
 
 //===----------------------------------------------------------------------===//
 // PowerPC QPX Intrinsics.
 //
 
 let TargetPrefix = "ppc" in {  // All PPC intrinsics start with "llvm.ppc.".
   /// PowerPC_QPX_Intrinsic - Base class for all QPX intrinsics.

lib/Target/PowerPC/PPCInstrVSX.td

let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   // Vector Extract Unsigned Word
   def XXEXTRACTUW : XX2_RD6_UIM5_RS6<60, 165,
                                   (outs vsfrc:$XT), (ins vsrc:$XB, u4imm:$UIMM),
                                   "xxextractuw $XT, $XB, $UIMM", IIC_VecFP, []>;
   } // UseVSXReg = 1
 
   // Vector Insert Exponent DP/SP
   def XVIEXPDP : XX3_XT5_XA5_XB5<60, 248, "xviexpdp", vsrc, vsrc, vsrc,
-                                 IIC_VecFP, []>;
+    IIC_VecFP, [(set v2f64: $XT,(int_ppc_vsx_xviexpdp v2i64:$XA, v2i64:$XB))]>;
   def XVIEXPSP : XX3_XT5_XA5_XB5<60, 216, "xviexpsp", vsrc, vsrc, vsrc,
-                                 IIC_VecFP, []>;
+    IIC_VecFP, [(set v4f32: $XT,(int_ppc_vsx_xviexpsp v4i32:$XA, v4i32:$XB))]>;
 
   // Vector Extract Exponent/Significand DP/SP
   def XVXEXPDP : XX2_XT6_XO5_XB6<60,  0, 475, "xvxexpdp", vsrc, []>;
   def XVXEXPSP : XX2_XT6_XO5_XB6<60,  8, 475, "xvxexpsp", vsrc, []>;
   def XVXSIGDP : XX2_XT6_XO5_XB6<60,  1, 475, "xvxsigdp", vsrc, []>;
   def XVXSIGSP : XX2_XT6_XO5_XB6<60,  9, 475, "xvxsigsp", vsrc, []>;
 
   //===--------------------------------------------------------------------===//

test/CodeGen/PowerPC/vsx-p9.ll

 ; CHECK: lxvx 0, 0, 3
 ; CHECK: lxvx 1, 0, 4
 ; CHECK: xvadddp 0, 0, 1
 ; CHECK: stxvx 0,
 ; CHECK: bl sink
   ret void
 }
 
+; Function Attrs: nounwind readnone
+define <4 x float> @testXVIEXPSP(<4 x i32> %a, <4 x i32> %b) {
+entry:
+  %0 = tail call <4 x float> @llvm.ppc.vsx.xviexpsp(<4 x i32> %a, <4 x i32> %b)
+  ret <4 x float> %0
+; CHECK-LABEL: testXVIEXPSP
+; CHECK: xviexpsp 34, 34, 35
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <4 x float> @llvm.ppc.vsx.xviexpsp(<4 x i32>, <4 x i32>)
+
+; Function Attrs: nounwind readnone
+define <2 x double> @testXVIEXPDP(<2 x i64> %a, <2 x i64> %b) {
+entry:
+  %0 = tail call <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64> %a, <2 x i64> %b)
+  ret <2 x double> %0
+; CHECK-LABEL: testXVIEXPDP
+; CHECK: xviexpdp 34, 34, 35
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64>, <2 x i64>)
+
 declare void @sink(...)