[ARM] Do not generate UMAAL instruction on thumbv7m target.

[pftbest]

Summary

UMAAL is a DSP instruction and it is not available on thumbv7m (Cortex-M3) and thumbv6m (Cortex-M0+1) targets.

Also fix wrong CHECK prefix in longMAC.ll test.

[jmolloy]

Hi,

Thanks for this! I'm going to approve, but please could you add another test checking that the UMAAL *does* get generated when targetting Cortex-M4 which is V7M+DSP.

Thanks!

James

[pftbest]

Added test for thumbv7em (Cortex-M4) target.

[jmolloy]

A thousand thanks. LGTM!

[pftbest]

If anyone has svn access, please commit.

[pftbest]

ping

[samparker]

Sorry, didn't see this. Will do!

[pftbest]

I think there is something wrong with the last line in the commit, looks like line ending is missing

[pftbest]

I didn't make this change in my diff.

[samparker]

Thanks for the heads up, please see review: D26027

lib/Target/ARM/ARMISelDAGToDAG.cpp

SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
                       getAL(CurDAG, dl),
                       CurDAG->getRegister(0, MVT::i32) };
     ReplaceNode(N, CurDAG->getMachineNode(Opc, dl, MVT::i32, MVT::i32, Ops));
     return;
   }
   case ARMISD::UMLAL:{
     // UMAAL is similar to UMLAL but it adds two 32-bit values to the
     // 64-bit multiplication result.
-    if (Subtarget->hasV6Ops() && N->getOperand(2).getOpcode() == ARMISD::ADDC &&
+    if (Subtarget->hasV6Ops() && Subtarget->hasDSP() &&
+        N->getOperand(2).getOpcode() == ARMISD::ADDC &&
         N->getOperand(3).getOpcode() == ARMISD::ADDE) {
 
       SDValue Addc = N->getOperand(2);
       SDValue Adde = N->getOperand(3);
 
       if (Adde.getOperand(2).getNode() == Addc.getNode()) {
 
         ConstantSDNode *Op0 = dyn_cast<ConstantSDNode>(Adde.getOperand(0));

lib/Target/ARM/ARMISelLowering.cpp

static SDValue AddCombineTo64bitUMAAL(SDNode *AddcNode,
                                       TargetLowering::DAGCombinerInfo &DCI,
                                       const ARMSubtarget *Subtarget) {
   // UMAAL is similar to UMLAL except that it adds two unsigned values.
   // While trying to combine for the other MLAL nodes, first search for the
   // chance to use UMAAL. Check if Addc uses another addc node which can first
   // be combined into a UMLAL. The other pattern is AddcNode being combined
   // into an UMLAL and then using another addc is handled in ISelDAGToDAG.
 
-  if (!Subtarget->hasV6Ops() ||
+  if (!Subtarget->hasV6Ops() || !Subtarget->hasDSP() ||
       (Subtarget->isThumb() && !Subtarget->hasThumb2()))
     return AddCombineTo64bitMLAL(AddcNode, DCI, Subtarget);
 
   SDNode *PrevAddc = nullptr;
   if (AddcNode->getOperand(0).getOpcode() == ISD::ADDC)
     PrevAddc = AddcNode->getOperand(0).getNode();
   else if (AddcNode->getOperand(1).getOpcode() == ISD::ADDC)
     PrevAddc = AddcNode->getOperand(1).getNode();

test/CodeGen/ARM/longMAC.ll

 ; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s -check-prefix=CHECK --check-prefix=CHECK-LE
 ; RUN: llc -mtriple=armv7-eabi %s -o - | FileCheck %s --check-prefix=CHECK-V7-LE
 ; RUN: llc -mtriple=armeb-eabi %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
 ; RUN: llc -mtriple=armebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-BE
 ; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V6-THUMB
 ; RUN: llc -mtriple=thumbv6t2-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V6-THUMB2
 ; RUN: llc -mtriple=thumbv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-THUMB
 ; RUN: llc -mtriple=thumbebv7-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7-THUMB-BE
+; RUN: llc -mtriple=thumbv6m-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V6M-THUMB
+; RUN: llc -mtriple=thumbv7m-eabi %s -o - | FileCheck %s -check-prefix=CHECK-V7M-THUMB
 ; Check generated signed and unsigned multiply accumulate long.
 
 define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
 ;CHECK-LABEL: MACLongTest1:
 ;CHECK-V6-THUMB-NOT: umlal
 ;CHECK-LE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-LE: mov r0, [[RDLO]]
 ;CHECK-LE: mov r1, [[RDHI]]
 ;CHECK-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-BE: mov r0, [[RDHI]]
 ;CHECK-BE: mov r1, [[RDLO]]
 ;CHECK-V6-THUMB2: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-V6-THUMB2: mov r0, [[RDLO]]
 ;CHECK-V6-THUMB2: mov r1, [[RDHI]]
-;CHECK-V7-THUMB2: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
-;CHECK-V7-THUMB2: mov r0, [[RDLO]]
-;CHECK-V7-THUMB2: mov r1, [[RDHI]]
-;CHECK-V7-THUMB2-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
-;CHECK-V7-THUMB2-BE: mov r0, [[RDHI]]
-;CHECK-V7-THUMB2-BE: mov r1, [[RDLO]]
+;CHECK-V7-THUMB: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
+;CHECK-V7-THUMB: mov r0, [[RDLO]]
+;CHECK-V7-THUMB: mov r1, [[RDHI]]
+;CHECK-V7-THUMB-BE: umlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
+;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
+;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
   %conv = zext i32 %a to i64
   %conv1 = zext i32 %b to i64
   %mul = mul i64 %conv1, %conv
   %add = add i64 %mul, %c
   ret i64 %add
 }
 
 define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c)  {
 ;CHECK-LABEL: MACLongTest2:
 ;CHECK-LE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-LE: mov r0, [[RDLO]]
 ;CHECK-LE: mov r1, [[RDHI]]
 ;CHECK-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-BE: mov r0, [[RDHI]]
 ;CHECK-BE: mov r1, [[RDLO]]
 ;CHECK-V6-THUMB2: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-V6-THUMB2: mov r0, [[RDLO]]
 ;CHECK-V6-THUMB2: mov r1, [[RDHI]]
-;CHECK-V7-THUMB2: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
-;CHECK-V7-THUMB2: mov r0, [[RDLO]]
-;CHECK-V7-THUMB2: mov r1, [[RDHI]]
-;CHECK-V7-THUMB2-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
-;CHECK-V7-THUMB2-BE: mov r0, [[RDHI]]
-;CHECK-V7-THUMB2-BE: mov r1, [[RDLO]]
+;CHECK-V7-THUMB: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
+;CHECK-V7-THUMB: mov r0, [[RDLO]]
+;CHECK-V7-THUMB: mov r1, [[RDHI]]
+;CHECK-V7-THUMB-BE: smlal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
+;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
+;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
   %conv = sext i32 %a to i64
   %conv1 = sext i32 %b to i64
   %mul = mul nsw i64 %conv1, %conv
   %add = add nsw i64 %mul, %c
   ret i64 %add
 }
 
 ; Two things to check here: the @earlyclobber constraint (on <= v5) and the "$Rd = $R" ones.

 ;CHECK-V7-THUMB: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-V7-THUMB: mov r0, [[RDLO]]
 ;CHECK-V7-THUMB: mov r1, [[RDHI]]
 ;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
 ;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
 ;CHECK-NOT:umaal
 ;CHECK-V6-THUMB-NOT: umaal
+;CHECK-V6M-THUMB-NOT: umaal
+;CHECK-V7M-THUMB-NOT: umaal
   %conv = zext i32 %lhs to i64
   %conv1 = zext i32 %rhs to i64
   %mul = mul nuw i64 %conv1, %conv
   %conv2 = zext i32 %lo to i64
   %add = add i64 %mul, %conv2
   %conv3 = zext i32 %hi to i64
   %add2 = add i64 %add, %conv3
   ret i64 %add2

 ;CHECK-V7-THUMB: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-V7-THUMB: mov r0, [[RDLO]]
 ;CHECK-V7-THUMB: mov r1, [[RDHI]]
 ;CHECK-V7-THUMB-BE: umaal [[RDLO:r[0-9]+]], [[RDHI:r[0-9]+]], [[LHS:r[0-9]+]], [[RHS:r[0-9]+]]
 ;CHECK-V7-THUMB-BE: mov r0, [[RDHI]]
 ;CHECK-V7-THUMB-BE: mov r1, [[RDLO]]
 ;CHECK-NOT:umaal
 ;CHECK-V6-THUMB-NOT:umaal
+;CHECK-V6M-THUMB-NOT: umaal
+;CHECK-V7M-THUMB-NOT: umaal
   %conv = zext i32 %lhs to i64
   %conv1 = zext i32 %rhs to i64
   %mul = mul nuw i64 %conv1, %conv
   %conv2 = zext i32 %lo to i64
   %conv3 = zext i32 %hi to i64
   %add = add i64 %conv2, %conv3
   %add2 = add i64 %add, %mul
   ret i64 %add2
 }