Fix arm64 floating point register spill recording in UnwindPlan analysis

[jasonmolenda]

Summary

When we're creating an UnwindPlan for arm64 functions that spill a floating point register, we don't decode the vector register numbers correctly and we don't have a way to represent the fact that the lower 64-bits of the registers are being saved to the stack (as the AAPCS64 ABI dictates). The first fix is easiest, the second is a bit more involved. The patch I have here may be a bit controversial, I'd like feedback from Greg and Tamas.

RegisterInfos_arm64.h defines the eRegisterKindLLDB register numbers used on Linux, Darwin, and FreeBSD. It also defines the layout of these registers in the register context buffer.

I add the "w" pseudo registers to represent the low 32 bits of the "x" registers, and "s" and "d" registers to represent the low 32/64 bits of the "v" registers. I add definitions for how to find those pseudo registers in the register context in RegisterInfos_arm64.h. It's not possible to specify this in a bi-endian correct way, so I've renamed the table from "g_register_infos_arm64" to "g_register_infos_arm64_le". I used defines to pick the offset of the w, s, and d registers so it will be easy (by duplicating the table) to have a correct definition for big-endian if we add support for a target like that in the future.

I hoisted the register number definitions (the eRegisterKindLLDB register numbers) out of RegisterInfos_arm64.h into a separate file so they aren't co-mingled with the register context definitions. I have them in Utility/ARM64_LLDB_Registers.h currently.

I switched EmulateInstructionARM64 and TestArm64InstEmulation to create / test against unwind plans using the eRegisterKindLLDB register numbers because DWARF doesn't have codepoints defined for the "s" or "d" registers.

I fixed the STP register decoding in EmulateInstructionARM64 for the vector registers.

I added a unit test to test that these spill and restore instructions are included in the UnwindPlan correctly.

Here are some reasons why this patch isn't usable as-is.

First, Greg's objection is along the lines that it is not correct to have a generic eRegisterKindLLDB register table shared by multiple targets. Today all arm64 targets have the same reg set, but it's possible to imagine an arm64 Cortex-M core that might not have the vector registers, for instance. If such a target used a generic table that defines v0, it might try to display that register as zeros or give an error about how that register is unavailable or something.

Second, Tamas is going to notice that there's a fourth arm64 RegisterContext file - RegisterContextPOSIX_arm64 - and a header file already defining eRegisterKindLLDB register numbers for arm64 in lldb-arm64-register-enums.h (similar tables also exist for arm, s390x, x86, and mips with different ones for different targets). I'm duplicating that file. To be honest, I only just noticed that file right before I was writing up this patch and I didn't want to wait an extra day to roll the register definitions into one.

I don't have a strong preference for whether I keep the Utility/ARM64_LLDB_Registers.h or whether I add the w, s, and d register numbers to lldb-arm64-register-enums.h and use that.

[tberghammer]

A few high level comments:

• I have the feeling you ported much more code over to use the LLDB register numbers then it would be strictly necessary. I am not sure if it is good or bad as it can help us consolidate the confusion around the different register numbering schema but it icnreases the size of this patch by a lot and also adds a lot of new boilerplate code.
• I would prefer to keep lldb-arm64-register-enums.h over the new file you added as your code contains a lot of logic in ARM64_LLDB_Registers.cpp (e.g. to string conversion) what seems unnecessary to me as the register tables you modified recently already contains all information to get from register number to register name
• Regarding Greg's concern I think we should have a single table (RegisterInfoInterface) containing all registers what can appear on the target and then the register context should be the one who detects which one is available and then returns the correct one accordingly. We already have functionality like this for x86_64 where RegisterInfos_x86_64.h and lldb-x86-register-enums.h defines all possibly available register and then NativeRegisterContextLinux_x86_64 detects if the AVX and MPX registers are available or not and then report the register list accordingly.

In mid/long term I think we should clean up the full register info handling code to simplify all of this in the following lines (vague ideas):

• Implement a single copy of RegisterInfoInterface for every architecture what returns the correct list of registers based on the architecture and sub-architecture
• Define register sets inside the RegisterInfoInterface instead of inside the RegistrerContext... classes
• Change EmulateInstruction... to use the RegisterInfoInterface to get a RegisterInfo object from the register numbers
• Change all RegisterContext... to use the information from the RegisterInfoInterface... classes instead of duplicating it into them

Doing all of the cleanup will be a lot of work so I am not asking you to do it or I don't want to wait with this change for that long but wanted to raise it here so we don't start to move in a direction what will make later improvements more difficult

source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp

196–197

What do you think about teaching this function to handle both eRegisterKindDWARF and eRegisterKindLLDB? That way you can use both in the emulation code. Also that would me that you don't have to update all usage inside the emulation code.

source/Utility/ARM64_LLDB_Registers.cpp

18 ↗

(On Diff #75389)

I think this function is completely unnecessary if you use the g_register_infos_arm64_le table (or one of it's wrapper)

[jasonmolenda]

Hi Tamas, sorry for not replying earlier, something urgent came up that I needed to look at.

Thanks for the review. I agree with using your existing arm64 register enums in lldb-arm64-register-enums.h. I'd like to remove the enums in RegisterInfos_arm64.h instead of having two copies that could diverge.

You asked about having EmulateInstructionARM64 handle both eRegisterKindDWARF and eRegisterKindLLDB. I'm not sure how that would work - each UnwindPlan must can use only one register numbering scheme. We could use eRegisterKindDWARF if there were no floating point register save/restores - but that seems a bit complicated; we'd conditionally use eRegisterKindLLDB sometimes, eRegisterKindDWARF most of the time.

As for the GetRegisterName() function in ARM64_LLDB_Registers.cpp, we could have EmulateInstructionARM64 with the register file definition (we need to define seven preprocessor symbols before we can include RegisterInfos_arm64.h and then we'll need to write a GetRegisterName() method in EmulateInstructionARM64.cpp. Wouldn't it be clearer to have a lldb-arm64-register-enums.cpp with this method?

I was talking about these register numbering problems with Greg Clayton and he half-jokingly said we should switch from register numbers to using ConstString register names in the UnwindPlans. It's not a bad idea! As long as everyone can agree on the register names for an architecture, anyway.

[jasonmolenda]

I believe this rewrite of the original patch addresses Tamas' feedback (thanks Tamas!) I dropped a lot of the changes in the original; I switch EmulateInstructionARM64 from using DWARF register numbering to use LLDB register numbering and I am using the numbers from lldb-arm64-register-enums.h. I get the register definitions (size, etc) from RegisterInfos_arm64.h.

I also fix the original bug that I was doing this for - to recognize the callee saves of the floating point register spills. And added a unit test to test for that.

Tamas, when you have a minute could you look at this again and let me know what you think? Thanks.

[labath]

Tamas is not in this week. He should be back on monday.

[tberghammer]

The patch generally looks good to me. I added a few high level thought about register context but they are clearly out of scope for this change. Also next time please upload your patch with full context as it is much easier to review that way.

In D25864#578173, @jasonmolenda wrote:

Hi Tamas, sorry for not replying earlier, something urgent came up that I needed to look at.

Thanks for the review. I agree with using your existing arm64 register enums in lldb-arm64-register-enums.h. I'd like to remove the enums in RegisterInfos_arm64.h instead of having two copies that could diverge.

You asked about having EmulateInstructionARM64 handle both eRegisterKindDWARF and eRegisterKindLLDB. I'm not sure how that would work - each UnwindPlan must can use only one register numbering scheme. We could use eRegisterKindDWARF if there were no floating point register save/restores - but that seems a bit complicated; we'd conditionally use eRegisterKindLLDB sometimes, eRegisterKindDWARF most of the time.

My idea is based on the fact that every register access goes through the GetRegisterInfo function what gets a "register kind" and a "register number" so if we can teach that function to be able to fetch the correct register info both for eRegisterKindLLDB and for eRegisterKindDWARF then the actual emulate functions can use both. It would mean something like the following, but I don't know what should we put in place of the "...":

if (reg_kind == eRegisterKindLLDB)
  return LLDBTableGetRegisterInfo(reg_num, reg_info);
if (reg_kind == eRegisterKindDwarf)
  return ...

As for the GetRegisterName() function in ARM64_LLDB_Registers.cpp, we could have EmulateInstructionARM64 with the register file definition (we need to define seven preprocessor symbols before we can include RegisterInfos_arm64.h and then we'll need to write a GetRegisterName() method in EmulateInstructionARM64.cpp. Wouldn't it be clearer to have a lldb-arm64-register-enums.cpp with this method?

RegisterInfos_arm64.h already contains a register name and an alternative name so I would prefer to use them as they are already specified but I have no problem with having a GetRegisterName() function if we can have a single copy of it. My main problem with your previous approach was that you are adding a second copy of it (current one is in ARM64_DWARF_Registers.cpp)

Regarding including RegisterInfos_arm64.h I am not too keen on the approach of having a large table and defining a set of macros as it is very verbose and limits the flexibility (e.g. big/little endian issue we found recently) but I haven't come up with a better idea yet.

I was talking about these register numbering problems with Greg Clayton and he half-jokingly said we should switch from register numbers to using ConstString register names in the UnwindPlans. It's not a bad idea! As long as everyone can agree on the register names for an architecture, anyway.

Personally I really don't like ConstString because of the global pool behind it (kind of leaks memory) so I think having some sort of register number is better. I think a betetr approach would be to agree that inside LLDB everything should use eRegisterKindLLDB and we do the register number translation at the communication boundaries (gdb-remote communication, eh_frame parsing, dwarf reading)

[jasonmolenda]

Committed in r285662.

source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp

 
 #include "Plugins/Process/Utility/ARMDefines.h"
 #include "Plugins/Process/Utility/ARMUtils.h"
-#include "Utility/ARM64_DWARF_Registers.h"
+#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
 
+#define GPR_OFFSET(idx) ((idx)*8)
+#define GPR_OFFSET_NAME(reg) 0
+#define FPU_OFFSET(idx) ((idx)*16)
+#define FPU_OFFSET_NAME(reg) 0
+#define EXC_OFFSET_NAME(reg) 0
+#define DBG_OFFSET_NAME(reg) 0
+#define DBG_OFFSET_NAME(reg) 0
+#define DEFINE_DBG(re, y)                                                      \
+  "na", nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex,                  \
+      {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,          \
+       LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},                              \
+      nullptr, nullptr, nullptr, 0
+
+#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
+
+#include "Plugins/Process/Utility/RegisterInfos_arm64.h"
+
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/MathExtras.h" // for SignExtend32 template function
                                      // and CountTrailingZeros_32 function

 using namespace lldb;
 using namespace lldb_private;
 
+static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo &reg_info) {
+  if (reg_num >= llvm::array_lengthof(g_register_infos_arm64_le))
+    return false;
+  reg_info = g_register_infos_arm64_le[reg_num];
+  return true;
+}
+
 #define No_VFP 0
 #define VFPv1 (1u << 1)
 #define VFPv2 (1u << 2)

   if (reg_kind == eRegisterKindGeneric) {
     switch (reg_num) {
     case LLDB_REGNUM_GENERIC_PC:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = arm64_dwarf::pc;
+      reg_kind = eRegisterKindLLDB;
+      reg_num = gpr_pc_arm64;
       break;
     case LLDB_REGNUM_GENERIC_SP:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = arm64_dwarf::sp;
+      reg_kind = eRegisterKindLLDB;
+      reg_num = gpr_sp_arm64;
       break;
     case LLDB_REGNUM_GENERIC_FP:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = arm64_dwarf::fp;
+      reg_kind = eRegisterKindLLDB;
+      reg_num = gpr_fp_arm64;
       break;
     case LLDB_REGNUM_GENERIC_RA:
-      reg_kind = eRegisterKindDWARF;
-      reg_num = arm64_dwarf::lr;
+      reg_kind = eRegisterKindLLDB;
+      reg_num = gpr_lr_arm64;
       break;
     case LLDB_REGNUM_GENERIC_FLAGS:
-      // There is no DWARF register number for the CPSR right now...
-      reg_info.name = "cpsr";
-      reg_info.alt_name = NULL;
-      reg_info.byte_size = 4;
-      reg_info.byte_offset = 0;
-      reg_info.encoding = eEncodingUint;
-      reg_info.format = eFormatHex;
-      for (uint32_t i = 0; i < lldb::kNumRegisterKinds; ++i)
-        reg_info.kinds[reg_kind] = LLDB_INVALID_REGNUM;
-      reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
-      return true;
+      reg_kind = eRegisterKindLLDB;
+      reg_num = gpr_cpsr_arm64;
+      break;
 
     default:
       return false;

     }
   }
 
-  if (reg_kind == eRegisterKindDWARF)
-    return arm64_dwarf::GetRegisterInfo(reg_num, reg_info);
+  if (reg_kind == eRegisterKindLLDB)
+    return LLDBTableGetRegisterInfo(reg_num, reg_info);
   return false;
 }
 

   //    if (m_opcode_cpsr == 0 || m_ignore_conditions == false)
   //    {
   //        m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric,
-  //        // use eRegisterKindDWARF is we ever get a cpsr DWARF register
-  //        number
   //                                              LLDB_REGNUM_GENERIC_FLAGS,
-  //                                              // use arm64_dwarf::cpsr if we
-  //                                              ever get one
+  //                                              gpr_cpsr_arm64
   //                                              0,
   //                                              &success);
   //    }

   uint32_t orig_pc_value = 0;
   if (auto_advance_pc) {
     orig_pc_value =
-        ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::pc, 0, &success);
+        ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
     if (!success)
       return false;
   }

 
   if (auto_advance_pc) {
     uint32_t new_pc_value =
-        ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::pc, 0, &success);
+        ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_arm64, 0, &success);
     if (!success)
       return false;
 

       EmulateInstruction::Context context;
       context.type = eContextAdvancePC;
       context.SetNoArgs();
-      if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, arm64_dwarf::pc,
+      if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_arm64,
                                  orig_pc_value + 4))
         return false;
     }

 bool EmulateInstructionARM64::CreateFunctionEntryUnwind(
     UnwindPlan &unwind_plan) {
   unwind_plan.Clear();
-  unwind_plan.SetRegisterKind(eRegisterKindDWARF);
+  unwind_plan.SetRegisterKind(eRegisterKindLLDB);
 
   UnwindPlan::RowSP row(new UnwindPlan::Row);
 
   // Our previous Call Frame Address is the stack pointer
-  row->GetCFAValue().SetIsRegisterPlusOffset(arm64_dwarf::sp, 0);
+  row->GetCFAValue().SetIsRegisterPlusOffset(gpr_sp_arm64, 0);
 
   unwind_plan.AppendRow(row);
   unwind_plan.SetSourceName("EmulateInstructionARM64");
   unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
   unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
-  unwind_plan.SetReturnAddressRegister(arm64_dwarf::lr);
+  unwind_plan.SetReturnAddressRegister(gpr_lr_arm64);
   return true;
 }
 

   if (m_arch.GetTriple().isAndroid())
     return LLDB_INVALID_REGNUM; // Don't use frame pointer on android
 
-  return arm64_dwarf::fp;
+  return gpr_fp_arm64;
 }
 
 bool EmulateInstructionARM64::UsingAArch32() {

     return false; // UNDEFINED;
   }
   uint64_t result;
-  uint64_t operand1 = ReadRegisterUnsigned(eRegisterKindDWARF,
-                                           arm64_dwarf::x0 + n, 0, &success);
+  uint64_t operand1 =
+      ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
   uint64_t operand2 = imm;
   bit carry_in;
 

 
   Context context;
   RegisterInfo reg_info_Rn;
-  if (arm64_dwarf::GetRegisterInfo(n, reg_info_Rn))
+  if (GetRegisterInfo(eRegisterKindLLDB, n, reg_info_Rn))
     context.SetRegisterPlusOffset(reg_info_Rn, imm);
 
-  if (n == GetFramePointerRegisterNumber() && d == arm64_dwarf::sp &&
-      !setflags) {
+  if (n == GetFramePointerRegisterNumber() && d == gpr_sp_arm64 && !setflags) {
     // 'mov sp, fp' - common epilogue instruction, CFA is now in terms
     // of the stack pointer, instead of frame pointer.
     context.type = EmulateInstruction::eContextRestoreStackPointer;
-  } else if ((n == arm64_dwarf::sp || n == GetFramePointerRegisterNumber()) &&
-             d == arm64_dwarf::sp && !setflags) {
+  } else if ((n == gpr_sp_arm64 || n == GetFramePointerRegisterNumber()) &&
+             d == gpr_sp_arm64 && !setflags) {
     context.type = EmulateInstruction::eContextAdjustStackPointer;
-  } else if (d == GetFramePointerRegisterNumber() && n == arm64_dwarf::sp &&
+  } else if (d == GetFramePointerRegisterNumber() && n == gpr_sp_arm64 &&
              !setflags) {
     context.type = EmulateInstruction::eContextSetFramePointer;
   } else {

     context.type = EmulateInstruction::eContextImmediate;
   }
 
-  // If setflags && d == arm64_dwarf::sp then d = WZR/XZR. See CMN, CMP
-  if (!setflags || d != arm64_dwarf::sp)
-    WriteRegisterUnsigned(context, eRegisterKindDWARF, arm64_dwarf::x0 + d,
-                          result);
+  // If setflags && d == gpr_sp_arm64 then d = WZR/XZR. See CMN, CMP
+  if (!setflags || d != gpr_sp_arm64)
+    WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_x0_arm64 + d, result);
 
   return false;
 }

   RegisterInfo reg_info_base;
   RegisterInfo reg_info_Rt;
   RegisterInfo reg_info_Rt2;
-  if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + n, reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
     return false;
 
   if (vector) {
-    if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::v0 + n, reg_info_Rt))
+    if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t, reg_info_Rt))
       return false;
-    if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::v0 + n, reg_info_Rt2))
+    if (!GetRegisterInfo(eRegisterKindLLDB, fpu_d0_arm64 + t2, reg_info_Rt2))
       return false;
   } else {
-    if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + t, reg_info_Rt))
+    if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
       return false;
-    if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + t2,
-                         reg_info_Rt2))
+    if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t2, reg_info_Rt2))
       return false;
   }
 

   if (n == 31) {
     // CheckSPAlignment();
     address =
-        ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::sp, 0, &success);
+        ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
   } else
-    address = ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::x0 + n, 0,
-                                   &success);
+    address =
+        ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
 
   wb_address = address + idx;
   if (a_mode != AddrMode_POST)

 
   if (n == 31)
     address =
-        ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::sp, 0, &success);
+        ReadRegisterUnsigned(eRegisterKindLLDB, gpr_sp_arm64, 0, &success);
   else
-    address = ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::x0 + n, 0,
-                                   &success);
+    address =
+        ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + n, 0, &success);
 
   if (!success)
     return false;

     address += offset;
 
   RegisterInfo reg_info_base;
-  if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + n, reg_info_base))
+  if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + n, reg_info_base))
     return false;
 
   RegisterInfo reg_info_Rt;
-  if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + t, reg_info_Rt))
+  if (!GetRegisterInfo(eRegisterKindLLDB, gpr_x0_arm64 + t, reg_info_Rt))
     return false;
 
   Context context;

   switch (branch_type) {
   case BranchType_CALL: {
     addr_t x30 = pc + 4;
-    if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, arm64_dwarf::x30,
-                               x30))
+    if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_lr_arm64, x30))
       return false;
   } break;
   case BranchType_JMP:

   bool is_zero = Bit32(opcode, 24) == 0;
   int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2);
 
-  const uint64_t operand = ReadRegisterUnsigned(
-      eRegisterKindDWARF, arm64_dwarf::x0 + t, 0, &success);
+  const uint64_t operand =
+      ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
   if (!success)
     return false;
 

   uint32_t bit_val = Bit32(opcode, 24);
   int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2);
 
-  const uint64_t operand = ReadRegisterUnsigned(
-      eRegisterKindDWARF, arm64_dwarf::x0 + t, 0, &success);
+  const uint64_t operand =
+      ReadRegisterUnsigned(eRegisterKindLLDB, gpr_x0_arm64 + t, 0, &success);
   if (!success)
     return false;
 

unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp

 #include <vector>
 
 #include "Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h"
-#include "Utility/ARM64_DWARF_Registers.h"
 
 #include "lldb/Core/Address.h"
 #include "lldb/Core/AddressRange.h"

 
 #include "Plugins/Disassembler/llvm/DisassemblerLLVMC.h"
 #include "Plugins/Instruction/ARM64/EmulateInstructionARM64.h"
+#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
 #include "llvm/Support/TargetSelect.h"
 
 using namespace lldb;

   // CFA=sp +0
   row_sp = unwind_plan.GetRowForFunctionOffset(0);
   EXPECT_EQ(0ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 

   // CFA=sp+16 => fp=[CFA-16] lr=[CFA-8]
   row_sp = unwind_plan.GetRowForFunctionOffset(4);
   EXPECT_EQ(4ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-16, regloc.GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-8, regloc.GetOffset());
 

   // CFA=fp+16 => fp=[CFA-16] lr=[CFA-8]
   row_sp = unwind_plan.GetRowForFunctionOffset(8);
   EXPECT_EQ(8ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_fp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-16, regloc.GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-8, regloc.GetOffset());
 

   // CFA=sp+16 => fp=[CFA-16] lr=[CFA-8]
   row_sp = unwind_plan.GetRowForFunctionOffset(16);
   EXPECT_EQ(16ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-16, regloc.GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-8, regloc.GetOffset());
 

   // CFA=sp +0 => fp= <same> lr= <same>
   row_sp = unwind_plan.GetRowForFunctionOffset(20);
   EXPECT_EQ(20ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 }

   // 0: CFA=sp +0 =>
   row_sp = unwind_plan.GetRowForFunctionOffset(0);
   EXPECT_EQ(0ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 

   // 4: CFA=sp+48 => x21=[CFA-40] x22=[CFA-48]
   row_sp = unwind_plan.GetRowForFunctionOffset(4);
   EXPECT_EQ(4ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x21, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x21_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-40, regloc.GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x22, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x22_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-48, regloc.GetOffset());
 

   // 8: CFA=sp+48 => x19=[CFA-24] x20=[CFA-32] x21=[CFA-40] x22=[CFA-48]
   row_sp = unwind_plan.GetRowForFunctionOffset(8);
   EXPECT_EQ(8ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x19, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x19_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-24, regloc.GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x20_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-32, regloc.GetOffset());
 

   // fp=[CFA-16] lr=[CFA-8]
   row_sp = unwind_plan.GetRowForFunctionOffset(12);
   EXPECT_EQ(12ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-16, regloc.GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-8, regloc.GetOffset());
 

   // fp=[CFA-16] lr=[CFA-8]
   row_sp = unwind_plan.GetRowForFunctionOffset(16);
   EXPECT_EQ(16ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_fp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset());
 

   // fp=[CFA-16] lr=[CFA-8]
   row_sp = unwind_plan.GetRowForFunctionOffset(28);
   EXPECT_EQ(28ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset());
 

 
   // I'd prefer if these restored registers were cleared entirely instead of set
   // to IsSame...
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
   EXPECT_TRUE(regloc.IsSame());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
   EXPECT_TRUE(regloc.IsSame());
 
   // 36: CFA=sp+48 => x19= <same> x20= <same> x21=[CFA-40] x22=[CFA-48] fp=

   row_sp = unwind_plan.GetRowForFunctionOffset(36);
   EXPECT_EQ(36ull, row_sp->GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x19, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x19_arm64, regloc));
   EXPECT_TRUE(regloc.IsSame());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x20_arm64, regloc));
   EXPECT_TRUE(regloc.IsSame());
 
   // 40: CFA=sp +0 => x19= <same> x20= <same> x21= <same> x22= <same> fp= <same>

   // lr= <same>
   row_sp = unwind_plan.GetRowForFunctionOffset(40);
   EXPECT_EQ(40ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x21, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x21_arm64, regloc));
   EXPECT_TRUE(regloc.IsSame());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x22, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x22_arm64, regloc));
   EXPECT_TRUE(regloc.IsSame());
 }
 

   // 0: CFA=sp +0 =>
   row_sp = unwind_plan.GetRowForFunctionOffset(0);
   EXPECT_EQ(0ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 
   row_sp = unwind_plan.GetRowForFunctionOffset(32);
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x19, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x21, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x22, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x23, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x24, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x25, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x26, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x27, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x28, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc));
-  EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x19_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x20_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x21_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x22_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x23_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x24_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x25_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x26_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x27_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_x28_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_fp_arm64, regloc));
+  EXPECT_FALSE(row_sp->GetRegisterInfo(gpr_lr_arm64, regloc));
 
   row_sp = unwind_plan.GetRowForFunctionOffset(36);
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 
   row_sp = unwind_plan.GetRowForFunctionOffset(52);
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 
   row_sp = unwind_plan.GetRowForFunctionOffset(56);
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 
   row_sp = unwind_plan.GetRowForFunctionOffset(60);
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
 }

 
   row_sp = unwind_plan.GetRowForFunctionOffset(36);
   EXPECT_EQ(28ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_fp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x20_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-32, regloc.GetOffset());
 
   row_sp = unwind_plan.GetRowForFunctionOffset(40);
   EXPECT_EQ(28ull, row_sp->GetOffset());
-  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp);
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_fp_arm64);
   EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
   EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset());
 
-  EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc));
+  EXPECT_TRUE(row_sp->GetRegisterInfo(gpr_x20_arm64, regloc));
   EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
   EXPECT_EQ(-32, regloc.GetOffset());
 }
+
+TEST_F(TestArm64InstEmulation, TestRegisterDoubleSpills) {
+  ArchSpec arch("arm64-apple-ios10", nullptr);
+  UnwindAssemblyInstEmulation *engine =
+      static_cast<UnwindAssemblyInstEmulation *>(
+          UnwindAssemblyInstEmulation::CreateInstance(arch));
+  ASSERT_NE(nullptr, engine);
+
+  UnwindPlan::RowSP row_sp;
+  AddressRange sample_range;
+  UnwindPlan unwind_plan(eRegisterKindLLDB);
+  UnwindPlan::Row::RegisterLocation regloc;
+
+  // this file built with clang for iOS arch arm64 optimization -Os
+  // #include <stdio.h>
+  // double foo(double in) {
+  // double arr[32];
+  // for (int i = 0; i < 32; i++)
+  //   arr[i] = in + i;
+  // for (int i = 2; i < 30; i++)
+  //   arr[i] = ((((arr[i - 1] * arr[i - 2] * 0.2) + (0.7 * arr[i])) /
+  //   ((((arr[i] * 0.73) + 0.65) * (arr[i - 1] + 0.2)) - ((arr[i + 1] + (arr[i]
+  //   * 0.32) + 0.52) / 0.3) + (0.531 * arr[i - 2]))) + ((arr[i - 1] + 5) /
+  //   ((arr[i + 2] + 0.4) / arr[i])) + (arr[5] * (0.17 + arr[7] * arr[i])) +
+  //   ((i > 5 ? (arr[i - 3]) : arr[i - 1]) * 0.263) + (((arr[i - 2] + arr[i -
+  //   1]) * 0.3252) + 3.56) - (arr[i + 1] * 0.852311)) * ((arr[i] * 85234.1345)
+  //   + (77342.451324 / (arr[i - 2] + arr[i - 1] - 73425341.33455))) + (arr[i]
+  //   * 875712013.55) - (arr[i - 1] * 0.5555) - ((arr[i] * (arr[i + 1] +
+  //   17342834.44) / 8688200123.555)) + (arr[i - 2] + 8888.888);
+  // return arr[16];
+  //}
+  // int main(int argc, char **argv) { printf("%g\n", foo(argc)); }
+
+  // so function foo() uses enough registers that it spills the callee-saved
+  // floating point registers.
+  uint8_t data[] = {
+      // prologue
+      0xef, 0x3b, 0xba, 0x6d, //  0: 0x6dba3bef   stp    d15, d14, [sp, #-0x60]!
+      0xed, 0x33, 0x01, 0x6d, //  4: 0x6d0133ed   stp    d13, d12, [sp, #0x10]
+      0xeb, 0x2b, 0x02, 0x6d, //  8: 0x6d022beb   stp    d11, d10, [sp, #0x20]
+      0xe9, 0x23, 0x03, 0x6d, // 12: 0x6d0323e9   stp    d9, d8, [sp, #0x30]
+      0xfc, 0x6f, 0x04, 0xa9, // 16: 0xa9046ffc   stp    x28, x27, [sp, #0x40]
+      0xfd, 0x7b, 0x05, 0xa9, // 20: 0xa9057bfd   stp    x29, x30, [sp, #0x50]
+      0xfd, 0x43, 0x01, 0x91, // 24: 0x910143fd   add    x29, sp, #0x50
+      0xff, 0x43, 0x04, 0xd1, // 28: 0xd10443ff   sub    sp, sp, #0x110
+
+      // epilogue
+      0xbf, 0x43, 0x01, 0xd1, // 32: 0xd10143bf   sub    sp, x29, #0x50
+      0xfd, 0x7b, 0x45, 0xa9, // 36: 0xa9457bfd   ldp    x29, x30, [sp, #0x50]
+      0xfc, 0x6f, 0x44, 0xa9, // 40: 0xa9446ffc   ldp    x28, x27, [sp, #0x40]
+      0xe9, 0x23, 0x43, 0x6d, // 44: 0x6d4323e9   ldp    d9, d8, [sp, #0x30]
+      0xeb, 0x2b, 0x42, 0x6d, // 48: 0x6d422beb   ldp    d11, d10, [sp, #0x20]
+      0xed, 0x33, 0x41, 0x6d, // 52: 0x6d4133ed   ldp    d13, d12, [sp, #0x10]
+      0xef, 0x3b, 0xc6, 0x6c, // 56: 0x6cc63bef   ldp    d15, d14, [sp], #0x60
+      0xc0, 0x03, 0x5f, 0xd6, // 60: 0xd65f03c0   ret
+  };
+
+  // UnwindPlan we expect:
+  //   0: CFA=sp +0 =>
+  //   4: CFA=sp+96 => d14=[CFA-88] d15=[CFA-96]
+  //   8: CFA=sp+96 => d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  //  12: CFA=sp+96 => d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80]
+  //  d14=[CFA-88] d15=[CFA-96]
+  //  16: CFA=sp+96 => d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64]
+  //  d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  //  20: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] d8=[CFA-40] d9=[CFA-48]
+  //  d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80] d14=[CFA-88]
+  //  d15=[CFA-96]
+  //  24: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8]
+  //  d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72]
+  //  d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  //  28: CFA=fp+16 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8]
+  //  d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72]
+  //  d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  //  36: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8]
+  //  d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72]
+  //  d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  //  40: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] d8=[CFA-40] d9=[CFA-48]
+  //  d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80] d14=[CFA-88]
+  //  d15=[CFA-96]
+  //  44: CFA=sp+96 => d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64]
+  //  d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  //  48: CFA=sp+96 => d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80]
+  //  d14=[CFA-88] d15=[CFA-96]
+  //  52: CFA=sp+96 => d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  //  56: CFA=sp+96 => d14=[CFA-88] d15=[CFA-96]
+  //  60: CFA=sp +0 =>
+
+  sample_range = AddressRange(0x1000, sizeof(data));
+
+  EXPECT_TRUE(engine->GetNonCallSiteUnwindPlanFromAssembly(
+      sample_range, data, sizeof(data), unwind_plan));
+
+  //  28: CFA=fp+16 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8]
+  //  d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72]
+  //  d13=[CFA-80] d14=[CFA-88] d15=[CFA-96]
+  row_sp = unwind_plan.GetRowForFunctionOffset(28);
+  EXPECT_EQ(28ull, row_sp->GetOffset());
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_fp_arm64);
+  EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
+  EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d15_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-96, regloc.GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d14_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-88, regloc.GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d13_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-80, regloc.GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d12_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-72, regloc.GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d11_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-64, regloc.GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d10_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-56, regloc.GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d9_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-48, regloc.GetOffset());
+
+  EXPECT_TRUE(row_sp->GetRegisterInfo(fpu_d8_arm64, regloc));
+  EXPECT_TRUE(regloc.IsAtCFAPlusOffset());
+  EXPECT_EQ(-40, regloc.GetOffset());
+
+  //  60: CFA=sp +0 =>
+  row_sp = unwind_plan.GetRowForFunctionOffset(60);
+  EXPECT_EQ(60ull, row_sp->GetOffset());
+  EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == gpr_sp_arm64);
+  EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true);
+  EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset());
+
+  if (row_sp->GetRegisterInfo(fpu_d8_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(fpu_d9_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(fpu_d10_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(fpu_d11_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(fpu_d12_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(fpu_d13_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(fpu_d14_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(fpu_d15_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(gpr_x27_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+  if (row_sp->GetRegisterInfo(gpr_x28_arm64, regloc))
+    EXPECT_TRUE(regloc.IsSame());
+}