X86: Improve BT instruction selection for 64-bit values.

[pcc]

Summary

If a 64-bit value is tested against a bit which is known to be in the range
[0..32) (modulo 64), we can use the 32-bit BT instruction, which has a slightly
shorter encoding.

[RKSimon]

llvm/lib/Target/X86/X86ISelLowering.cpp

15317

Would this be cleaner with DAG.MaskedValueIsZero()?

[pcc]

Use MaskedValueIsZero

llvm/lib/Target/X86/X86ISelLowering.cpp

15317

Yes, done.

[spatel]

LGTM.
Although it seems like this could be a universal strength reduction optimization in IR. Ie, we should shrink these ops with the help of the datalayout in InstCombine?

llvm/lib/Target/X86/X86ISelLowering.cpp

static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
   // If Src is i8, promote it to i32 with any_extend.  There is no i8 BT
   // instruction.  Since the shift amount is in-range-or-undefined, we know
   // that doing a bittest on the i32 value is ok.  We extend to i32 because
   // the encoding for the i16 version is larger than the i32 version.
   // Also promote i16 to i32 for performance / code size reason.
   if (Src.getValueType() == MVT::i8 || Src.getValueType() == MVT::i16)
     Src = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Src);
 
+  // See if we can use the 32-bit instruction instead of the 64-bit one for a
+  // shorter encoding. Since the former takes the modulo 32 of BitNo and the
+  // latter takes the modulo 64, this is only valid if the 5th bit of BitNo is
+  // known to be zero.
+  if (Src.getValueType() == MVT::i64) {
+    APInt Zeros, Ones;
+    DAG.computeKnownBits(BitNo, Zeros, Ones);
+    if (Zeros[5])
+      Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
+  }
+
   // If the operand types disagree, extend the shift amount to match.  Since
   // BT ignores high bits (like shifts) we can use anyextend.
   if (Src.getValueType() != BitNo.getValueType())
     BitNo = DAG.getNode(ISD::ANY_EXTEND, dl, Src.getValueType(), BitNo);
 
   SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, Src, BitNo);
   X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;
   return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,

llvm/test/CodeGen/X86/bt.ll

 ;
   %neg = xor i32 %flags, -1
   %shl = shl i32 1, %flag
   %and = and i32 %shl, %neg
   %tobool = icmp ne i32 %and, 0
   ret i1 %tobool
 }
 
+define zeroext i1 @extend(i32 %bit, i64 %bits) {
+; CHECK-LABEL: extend:
+; CHECK:       # BB#0:
+; CHECK-NEXT:  btl %edi, %esi
+entry:
+  %and = and i32 %bit, 31
+  %sh_prom = zext i32 %and to i64
+  %shl = shl i64 1, %sh_prom
+  %and1 = and i64 %shl, %bits
+  %tobool = icmp ne i64 %and1, 0
+  ret i1 %tobool
+}