[AVX-512] Disassembler support for rounding control and SAE attribute.

[maksfb]

Summary

Add missing disassembler support for EVEX-encoded instructions with rounding control and/or SAE attribute.

[craig.topper]

I think this looks ok, but I'd like Elena to look at it too.

[maksfb]

@delena : could you please take a look?

[delena]

lib/Target/X86/X86InstrAVX512.td

1886

I don't see LIG specification in the "sae" form of VCMP:

EVEX.NDS.512.66.0F.W1 C2 /r ib FV V/V AVX512F Compare packed double-precision floating-point values
in zmm3/m512/m64bcst and zmm2 using bits 4:0 of
imm8 as a comparison predicate with writemask k2
and leave the result in mask register k1.
VCMPPD k1 {k2}, zmm2,
zmm3/m512/m64bcst{sae}, imm8

5817

Why do you need to remove EVEX_V512 from the second pattern?

[maksfb]

lib/Target/X86/X86InstrAVX512.td

1886

The spec for SAE says it "applies to scalar and 512-bit vector lengths". I don't know how CPU actually treats L'L when {sae} is set, except that LLVM assembler generates {0,0}, not {1,0} that corresponds to 512-bit length.

As a result if you feed assembler output to disassembler it causes disassembler to fail.

I can speculate that LIG is implied in this case, but folks at Intel would know better. Could you check?

5817

Because RC implies 512-bit length ("Vector Length Orthogonality"), and putting EVEX_V512 enforces disassembler to accept L'L={1,0} only, while LLVM assembler generates {0,0} IIRC.

[delena]

lib/Target/X86/X86InstrAVX512.td

1886

According to table 4-7 in the spec:
FP Instructions w/o rounding semantic:
EVEX_B - SAE control
EVEX.L’L 00, 01, 10 - for 128/256/512.

5817

I read the spec again. "When EVEX is used to encode scalar instructions, L’L is generally ignored"
It means that you can put VEX_LIG to all scalars and remove EVEX_V512 from all scalar forms, right?

utils/TableGen/X86RecognizableInstr.cpp

996

Why IMM8 ?

[maksfb]

lib/Target/X86/X86InstrAVX512.td

1886

Does it make the spec wrong? Is there any non-512-bit vector instruction with SAE?

5817

Probably.

utils/TableGen/X86RecognizableInstr.cpp

996

Made more sense than IMM32 since it saves some bytes.

[delena]

lib/Target/X86/X86InstrAVX512.td

1886

1. You actually changed instruction encoding. We have a lot of encoding tests. Do you want to say that our tests do not cover these cases?
2. Could you, please, check what encoding is generated by GCC?
3. In order to be sure that the HW ignores L'L you can check with XED or SDE. XED is a part of SDE package which is free on Intel site.

utils/TableGen/X86RecognizableInstr.cpp

996

Where?

[maksfb]

I think the focus should be on fixing the state of LLVM's disassembler for AVX-512. While there could be issues with the encoder too, and it's important to find out if indeed the encoder has to be fixed, that has to be handled separately. This diff fixes multiple failures of LLVM disassembler while handling binaries with AVX-512, but it does not fix them all.

Since you have encoding tests - you can pass the output of assembler to disassembler. It's one line in .test file(s).

lib/Target/X86/X86InstrAVX512.td

1886

1. How? If you think I've changed the encoding could you provide an example? Do you have a test case that checks SAE encoding? What does it expect L'L to be? I'm based on rev from Oct 11th and all tests pass.
2. as from binutils 2.26.1 generates {0,0}.
3. I agree, it's important to make sure LLVM codegen for Intel's extension is not broken.

[delena]

Can you send me old and new encoding of vmpps with {sae}?
I'll try to check.

I also sent a question to our architects.

[delena]

Why do you need VEX_LIG for disassembler?
EVEX_B in reg-reg form says that you have SAE.
EVEX_RC says that you have RC.

[craig.topper]

I agree with Elena, we should use the other flags to ignore the vector size in the disassembler table generation. This is what we already do in the encoder. Let's keep the intention of the L and L2 bits in TSFlags as they are.

lib/Target/X86/Disassembler/X86Disassembler.cpp

static bool translateOperand(MCInst &mcInst, const OperandSpecifier &operand,
   CASE_ENCODING_RM:
     return translateRM(mcInst, operand, insn, Dis);
   case ENCODING_IB:
   case ENCODING_IW:
   case ENCODING_ID:
   case ENCODING_IO:
   case ENCODING_Iv:
   case ENCODING_Ia:
+  case ENCODING_Irc:
     translateImmediate(mcInst,
                        insn.immediates[insn.numImmediatesTranslated++],
                        operand,
                        insn,
                        Dis);
     return false;
   case ENCODING_SI:
     return translateSrcIndex(mcInst, insn);

lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp

for (const auto &Op : x86OperandSets[insn->spec->operands]) {
     case ENCODING_Iv:
       if (readImmediate(insn, insn->immediateSize))
         return -1;
       break;
     case ENCODING_Ia:
       if (readImmediate(insn, insn->addressSize))
         return -1;
       break;
+    case ENCODING_Irc:
+      // AVX512 rc is encoded in L'L bits.
+      insn->immediates[insn->numImmediatesConsumed] =
+        (l2FromEVEX4of4(insn->vectorExtensionPrefix[3]) << 1) |
+         lFromEVEX4of4(insn->vectorExtensionPrefix[3]);
+      ++insn->numImmediatesConsumed;
+      break;
     case ENCODING_RB:
       if (readOpcodeRegister(insn, 1))
         return -1;
       break;
     case ENCODING_RW:
       if (readOpcodeRegister(insn, 2))
         return -1;
       break;

lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h

#define ENCODINGS                                                              \
   ENUM_ENTRY(ENCODING_RW,     "(AX..DI, R8W..R15W)")                           \
   ENUM_ENTRY(ENCODING_RD,     "(EAX..EDI, R8D..R15D)")                         \
   ENUM_ENTRY(ENCODING_RO,     "(RAX..RDI, R8..R15)")                           \
   ENUM_ENTRY(ENCODING_FP,     "Position on floating-point stack in ModR/M "    \
                               "byte.")                                         \
                                                                                \
   ENUM_ENTRY(ENCODING_Iv,     "Immediate of operand size")                     \
   ENUM_ENTRY(ENCODING_Ia,     "Immediate of address size")                     \
+  ENUM_ENTRY(ENCODING_Irc,    "Immediate for static rounding control")         \
   ENUM_ENTRY(ENCODING_Rv,     "Register code of operand size added to the "    \
                               "opcode byte")                                   \
   ENUM_ENTRY(ENCODING_DUP,    "Duplicate of another operand; ID is encoded "   \
                               "in type")                                       \
   ENUM_ENTRY(ENCODING_SI,     "Source index; encoded in OpSize/Adsize prefix") \
   ENUM_ENTRY(ENCODING_DI,     "Destination index; encoded in prefixes")
 
 #define ENUM_ENTRY(n, d) n,

lib/Target/X86/X86InstrAVX512.td

multiclass avx512_vcmp_sae<X86VectorVTInfo _> {
   // comparison code form (VCMP[EQ/LT/LE/...]
   defm  rrib  : AVX512_maskable_cmp<0xC2, MRMSrcReg, _,
                      (outs _.KRC:$dst),(ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
                      "vcmp${cc}"#_.Suffix,
                      "{sae}, $src2, $src1", "$src1, $src2, {sae}",
                      (X86cmpmRnd (_.VT _.RC:$src1),
                                     (_.VT _.RC:$src2),
                                     imm:$cc,
-                                (i32 FROUND_NO_EXC))>, EVEX_B;
+                                (i32 FROUND_NO_EXC))>, VEX_LIG, EVEX_B;
 
   let isAsmParserOnly = 1, hasSideEffects = 0 in {
     defm  rrib_alt  : AVX512_maskable_cmp_alt<0xC2, MRMSrcReg, _,
                          (outs _.KRC:$dst),
                          (ins _.RC:$src1, _.RC:$src2, u8imm:$cc),
                          "vcmp"#_.Suffix,
                          "$cc, {sae}, $src2, $src1",
-                         "$src1, $src2, {sae}, $cc">, EVEX_B;
+                         "$src1, $src2, {sae}, $cc">, VEX_LIG, EVEX_B;
    }
 }
 
 multiclass avx512_vcmp<AVX512VLVectorVTInfo _> {
   let Predicates = [HasAVX512] in {
-    defm Z    : avx512_vcmp_common<_.info512>,
-                avx512_vcmp_sae<_.info512>, EVEX_V512;
+    defm Z    : avx512_vcmp_common<_.info512>, EVEX_V512;
+    defm Z    : avx512_vcmp_sae<_.info512>;
 
   }
   let Predicates = [HasAVX512,HasVLX] in {
    defm Z128 : avx512_vcmp_common<_.info128>, EVEX_V128;
    defm Z256 : avx512_vcmp_common<_.info256>, EVEX_V256;
   }
 }
 

 multiclass avx512_fp_scalar_round<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
                          SDNode VecNode, OpndItins itins, bit IsCommutable = 0> {
   let ExeDomain = _.ExeDomain in
   defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                           (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr,
                           "$rc, $src2, $src1", "$src1, $src2, $rc",
                           (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
                           (i32 imm:$rc)), itins.rr, IsCommutable>,
-                          EVEX_B, EVEX_RC;
+                          VEX_LIG, EVEX_B, EVEX_RC;
 }
 multiclass avx512_fp_scalar_sae<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
                          SDNode VecNode, OpndItins itins, bit IsCommutable> {
   let ExeDomain = _.ExeDomain in
   defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                             (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
                             "{sae}, $src2, $src1", "$src1, $src2, {sae}",
                             (VecNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
-                            (i32 FROUND_NO_EXC))>, EVEX_B;
+                            (i32 FROUND_NO_EXC))>, VEX_LIG, EVEX_B;
 }
 
 multiclass avx512_binop_s_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                   SDNode VecNode,
                                   SizeItins itins, bit IsCommutable> {
   defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
                               itins.s, IsCommutable>,
              avx512_fp_scalar_round<opc, OpcodeStr#"ss", f32x_info, VecNode,
                               itins.s, IsCommutable>,
-                              XS, EVEX_4V, VEX_LIG,  EVEX_CD8<32, CD8VT1>;
+                              XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
   defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
                               itins.d,                  IsCommutable>,
              avx512_fp_scalar_round<opc, OpcodeStr#"sd", f64x_info, VecNode,
                               itins.d, IsCommutable>,
-                              XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
+                              XD, VEX_W, EVEX_4V, EVEX_CD8<64, CD8VT1>;
 }
 
 multiclass avx512_binop_s_sae<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                   SDNode VecNode,
                                   SizeItins itins, bit IsCommutable> {
   defm SSZ : avx512_fp_scalar<opc, OpcodeStr#"ss", f32x_info, OpNode, VecNode,
                               itins.s, IsCommutable>,
              avx512_fp_scalar_sae<opc, OpcodeStr#"ss", f32x_info, VecNode,
                               itins.s, IsCommutable>,
-                              XS, EVEX_4V, VEX_LIG,  EVEX_CD8<32, CD8VT1>;
+                              XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
   defm SDZ : avx512_fp_scalar<opc, OpcodeStr#"sd", f64x_info, OpNode, VecNode,
                               itins.d,                  IsCommutable>,
              avx512_fp_scalar_sae<opc, OpcodeStr#"sd", f64x_info, VecNode,
                               itins.d, IsCommutable>,
-                              XD, VEX_W, EVEX_4V, VEX_LIG, EVEX_CD8<64, CD8VT1>;
+                              XD, VEX_W, EVEX_4V, EVEX_CD8<64, CD8VT1>;
 }
 defm VADD : avx512_binop_s_round<0x58, "vadd", fadd, X86faddRnd, SSE_ALU_ITINS_S, 1>;
 defm VMUL : avx512_binop_s_round<0x59, "vmul", fmul, X86fmulRnd, SSE_MUL_ITINS_S, 1>;
 defm VSUB : avx512_binop_s_round<0x5C, "vsub", fsub, X86fsubRnd, SSE_ALU_ITINS_S, 0>;
 defm VDIV : avx512_binop_s_round<0x5E, "vdiv", fdiv, X86fdivRnd, SSE_DIV_ITINS_S, 0>;
 defm VMIN : avx512_binop_s_sae  <0x5D, "vmin", X86fmin, X86fminRnd, SSE_ALU_ITINS_S, 0>;
 defm VMAX : avx512_binop_s_sae  <0x5F, "vmax", X86fmax, X86fmaxRnd, SSE_ALU_ITINS_S, 0>;
 
defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
                    (OpNode  _.RC:$src1, (_.VT (X86VBroadcast
                                               (_.ScalarLdFrag addr:$src2)))),
                    itins.rm>, EVEX_4V, EVEX_B;
   }
 }
 
 multiclass avx512_fp_round_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
                                   X86VectorVTInfo _> {
-  let ExeDomain = _.ExeDomain in
+  let ExeDomain = _.ExeDomain in {
   defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                   (ins _.RC:$src1, _.RC:$src2, AVX512RC:$rc), OpcodeStr##_.Suffix,
                   "$rc, $src2, $src1", "$src1, $src2, $rc",
                   (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 imm:$rc)))>,
-                  EVEX_4V, EVEX_B, EVEX_RC;
+                  VEX_LIG, EVEX_4V, EVEX_B, EVEX_RC;
+  }
 }
-
 
 multiclass avx512_fp_sae_packed<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd,
                                 X86VectorVTInfo _> {
   let ExeDomain = _.ExeDomain in
   defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                   (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
                   "{sae}, $src2, $src1", "$src1, $src2, {sae}",
                   (_.VT (OpNodeRnd _.RC:$src1, _.RC:$src2, (i32 FROUND_NO_EXC)))>,
let Predicates = [prd, HasVLX] in {
     defm PDZ256 : avx512_fp_packed<opc, OpcodeStr, OpNode, v4f64x_info,
                                    itins.d, IsCommutable>, EVEX_V256, PD, VEX_W,
                                    EVEX_CD8<64, CD8VF>;
   }
 }
 
 multiclass avx512_fp_binop_p_round<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
   defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
-                              EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
+                              PS, EVEX_CD8<32, CD8VF>;
   defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
-                              EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
+                              PD, VEX_W,EVEX_CD8<64, CD8VF>;
 }
 
 multiclass avx512_fp_binop_p_sae<bits<8> opc, string OpcodeStr, SDNode OpNodeRnd> {
   defm PSZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v16f32_info>,
-                              EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
+                              VEX_LIG, PS, EVEX_CD8<32, CD8VF>;
   defm PDZ : avx512_fp_sae_packed<opc, OpcodeStr, OpNodeRnd, v8f64_info>,
-                              EVEX_V512, PD, VEX_W,EVEX_CD8<64, CD8VF>;
+                              VEX_LIG, PD, VEX_W,EVEX_CD8<64, CD8VF>;
 }
 
 defm VADD : avx512_fp_binop_p<0x58, "vadd", fadd, HasAVX512,
                               SSE_ALU_ITINS_P, 1>,
             avx512_fp_binop_p_round<0x58, "vadd", X86faddRnd>;
 defm VMUL : avx512_fp_binop_p<0x59, "vmul", fmul, HasAVX512,
                               SSE_MUL_ITINS_P, 1>,
             avx512_fp_binop_p_round<0x59, "vmul", X86fmulRnd>;
defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
                   "$src2, $src1", "$src1, $src2",
                   (OpNode _.RC:$src1,
                           (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),
                           (i32 FROUND_CURRENT))>;
 }
 
 multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr, SDNode OpNode, SDNode OpNodeScal> {
   defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v16f32_info>,
-             avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
                               EVEX_V512, EVEX_CD8<32, CD8VF>;
+  defm PSZ : avx512_fp_round_packed<opc, OpcodeStr, OpNode, v16f32_info>,
+                              EVEX_CD8<32, CD8VF>;
   defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, v8f64_info>,
-             avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
                               EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
+  defm PDZ : avx512_fp_round_packed<opc, OpcodeStr, OpNode, v8f64_info>,
+                              VEX_W, EVEX_CD8<64, CD8VF>;
   defm SSZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f32x_info>,
                 avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNodeScal, SSE_ALU_ITINS_S.s>,
                               EVEX_4V,EVEX_CD8<32, CD8VT1>;
   defm SDZ128 : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, f64x_info>,
                 avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNodeScal, SSE_ALU_ITINS_S.d>,
                               EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
 
   // Define only if AVX512VL feature is present.

 
 multiclass avx512_fma3_213_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                  X86VectorVTInfo _, string Suff> {
   let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
   defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
           (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
           OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
           (_.VT ( OpNode _.RC:$src2, _.RC:$src1, _.RC:$src3, (i32 imm:$rc))), 1, 1>,
-          AVX512FMA3Base, EVEX_B, EVEX_RC;
+          AVX512FMA3Base, VEX_LIG, EVEX_B, EVEX_RC;
 }
 
 multiclass avx512_fma3p_213_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                    SDNode OpNodeRnd, AVX512VLVectorVTInfo _,
                                    string Suff> {
   let Predicates = [HasAVX512] in {
     defm Z      : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info512, Suff>,
-                  avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512,
-                      Suff>, EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
+                                      EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
+    defm Z      : avx512_fma3_213_round<opc, OpcodeStr, OpNodeRnd, _.info512,
+                      Suff>, EVEX_CD8<_.info512.EltSize, CD8VF>;
   }
   let Predicates = [HasVLX, HasAVX512] in {
     defm Z256 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info256, Suff>,
                       EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
     defm Z128 : avx512_fma3p_213_rm<opc, OpcodeStr, OpNode, _.info128, Suff>,
                       EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
   }
 }

 
 multiclass avx512_fma3_231_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                  X86VectorVTInfo _, string Suff> {
   let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
   defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
           (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
           OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
           (_.VT ( OpNode _.RC:$src2, _.RC:$src3, _.RC:$src1, (i32 imm:$rc))), 1, 1>,
-          AVX512FMA3Base, EVEX_B, EVEX_RC;
+          AVX512FMA3Base, VEX_LIG, EVEX_B, EVEX_RC;
 }
 
 multiclass avx512_fma3p_231_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                    SDNode OpNodeRnd, AVX512VLVectorVTInfo _,
                                    string Suff> {
   let Predicates = [HasAVX512] in {
     defm Z      : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info512, Suff>,
-                  avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512,
-                      Suff>, EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
+                                      EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
+    defm Z      : avx512_fma3_231_round<opc, OpcodeStr, OpNodeRnd, _.info512,
+                      Suff>, EVEX_CD8<_.info512.EltSize, CD8VF>;
   }
   let Predicates = [HasVLX, HasAVX512] in {
     defm Z256 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info256, Suff>,
                       EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
     defm Z128 : avx512_fma3p_231_rm<opc, OpcodeStr, OpNode, _.info128, Suff>,
                       EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
   }
 }

 
 multiclass avx512_fma3_132_round<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                  X86VectorVTInfo _, string Suff> {
   let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in
   defm rb: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
           (ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
           OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc",
           (_.VT ( OpNode _.RC:$src1, _.RC:$src3, _.RC:$src2, (i32 imm:$rc))), 1, 1>,
-          AVX512FMA3Base, EVEX_B, EVEX_RC;
+          AVX512FMA3Base, VEX_LIG, EVEX_B, EVEX_RC;
 }
 
 multiclass avx512_fma3p_132_common<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                    SDNode OpNodeRnd, AVX512VLVectorVTInfo _,
                                    string Suff> {
   let Predicates = [HasAVX512] in {
     defm Z      : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info512, Suff>,
-                  avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512,
-                      Suff>, EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
+                      EVEX_V512, EVEX_CD8<_.info512.EltSize, CD8VF>;
+    defm Z      : avx512_fma3_132_round<opc, OpcodeStr, OpNodeRnd, _.info512,
+                      Suff>, EVEX_CD8<_.info512.EltSize, CD8VF>;
   }
   let Predicates = [HasVLX, HasAVX512] in {
     defm Z256 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info256, Suff>,
                       EVEX_V256, EVEX_CD8<_.info256.EltSize, CD8VF>;
     defm Z128 : avx512_fma3p_132_rm<opc, OpcodeStr, OpNode, _.info128, Suff>,
                       EVEX_V128, EVEX_CD8<_.info128.EltSize, CD8VF>;
   }
 }
defm rrb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                         EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
                         EVEX_B, EVEX_RC;
 }
 multiclass avx512_cvt_fp_scalar_sd2ss<bits<8> opc, string OpcodeStr,
                                   SDNode OpNodeRnd, X86VectorVTInfo _src,
                                                         X86VectorVTInfo _dst> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
-             avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
-                               OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>,
-                               EVEX_V512, XD;
+                               VEX_W, EVEX_CD8<64, CD8VT1>, EVEX_V512, XD;
+    defm Z : avx512_cvt_fp_rc_scalar<opc, OpcodeStr, _dst, _src,
+                               OpNodeRnd>, VEX_W, EVEX_CD8<64, CD8VT1>, XD;
   }
 }
 
 multiclass avx512_cvt_fp_scalar_ss2sd<bits<8> opc, string OpcodeStr,
                                     SDNode OpNodeRnd, X86VectorVTInfo _src,
                                                           X86VectorVTInfo _dst> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_cvt_fp_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
-             avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
              EVEX_CD8<32, CD8VT1>, XS, EVEX_V512;
+    defm Z : avx512_cvt_fp_sae_scalar<opc, OpcodeStr, _dst, _src, OpNodeRnd>,
+             EVEX_CD8<32, CD8VT1>, XS;
   }
 }
 defm VCVTSD2SS : avx512_cvt_fp_scalar_sd2ss<0x5A, "vcvtsd2ss",
                                          X86froundRnd, f64x_info, f32x_info>;
 defm VCVTSS2SD : avx512_cvt_fp_scalar_ss2sd<0x5A, "vcvtss2sd",
                                           X86fpextRnd,f32x_info, f64x_info >;
 
 def : Pat<(f64 (fpextend FR32X:$src)),

 // Coversion with SAE - suppress all exceptions
 multiclass avx512_vcvt_fp_sae<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                          X86VectorVTInfo _Src, SDNode OpNodeRnd> {
   defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                         (ins _Src.RC:$src), OpcodeStr,
                         "{sae}, $src", "$src, {sae}",
                         (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src),
                                (i32 FROUND_NO_EXC)))>,
-                        EVEX, EVEX_B;
+                        VEX_LIG, EVEX, EVEX_B;
 }
 
 // Conversion with rounding control (RC)
 multiclass avx512_vcvt_fp_rc<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                          X86VectorVTInfo _Src, SDNode OpNodeRnd> {
   defm rrb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                         (ins _Src.RC:$src, AVX512RC:$rc), OpcodeStr,
                         "$rc, $src", "$src, $rc",
                         (_.VT (OpNodeRnd (_Src.VT _Src.RC:$src), (i32 imm:$rc)))>,
-                        EVEX, EVEX_B, EVEX_RC;
+                        VEX_LIG, EVEX, EVEX_B, EVEX_RC;
 }
 
 // Extend Float to Double
 multiclass avx512_cvtps2pd<bits<8> opc, string OpcodeStr> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8f32x_info, fpextend>,
-             avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
-                                X86vfpextRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_sae<opc, OpcodeStr, v8f64_info, v8f32x_info,
+                                X86vfpextRnd>;
   }
   let Predicates = [HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v4f32x_info,
                                X86vfpext, "{1to2}">, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4f32x_info, fpextend>,
                                      EVEX_V256;
   }
 }
 
 // Truncate Double to Float
 multiclass avx512_cvtpd2ps<bits<8> opc, string OpcodeStr> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fpround>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
-                               X86vfproundRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8f64_info,
+                               X86vfproundRnd>;
   }
   let Predicates = [HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2f64x_info,
                                X86vfpround, "{1to2}", "{x}">, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fpround,
                                "{1to4}", "{y}">, EVEX_V256;
   }
 }
multiclass avx512_cvtdq2pd<bits<8> opc, string OpcodeStr, SDNode OpNode,
   }
 }
 
 // Convert Signed/Unsigned Doubleword to Float
 multiclass avx512_cvtdq2ps<bits<8> opc, string OpcodeStr, SDNode OpNode,
                            SDNode OpNodeRnd> {
   let Predicates = [HasAVX512] in
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16f32_info, v16i32_info, OpNode>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v16f32_info, v16i32_info,
+                               OpNodeRnd>;
 
   let Predicates = [HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4i32x_info, OpNode>,
                                      EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i32x_info, OpNode>,
                                      EVEX_V256;
   }
 }
 
 // Convert Float to Signed/Unsigned Doubleword with truncation
 multiclass avx512_cvttps2dq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
-             avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
-                                OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_sae<opc, OpcodeStr, v16i32_info, v16f32_info,
+                                OpNodeRnd>;
   }
   let Predicates = [HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
                                      EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
                                      EVEX_V256;
   }
 }
 
 // Convert Float to Signed/Unsigned Doubleword
 multiclass avx512_cvtps2dq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i32_info, v16f32_info, OpNode>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
-                                OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v16i32_info, v16f32_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f32x_info, OpNode>,
                                      EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f32x_info, OpNode>,
                                      EVEX_V256;
   }
 }
 
 // Convert Double to Signed/Unsigned Doubleword with truncation
 multiclass avx512_cvttpd2dq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
-             avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
-                                OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_sae<opc, OpcodeStr, v8i32x_info, v8f64_info,
+                                OpNodeRnd>;
   }
   let Predicates = [HasVLX] in {
     // we need "x"/"y" suffixes in order to distinguish between 128 and 256
     // memory forms of these instructions in Asm Parcer. They have the same
     // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
     // due to the same reason.
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
                                "{1to2}", "{x}">, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
                                "{1to4}", "{y}">, EVEX_V256;
   }
 }
 
 // Convert Double to Signed/Unsigned Doubleword
 multiclass avx512_cvtpd2dq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasAVX512] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i32x_info, v8f64_info, OpNode>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v8i32x_info, v8f64_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasVLX] in {
     // we need "x"/"y" suffixes in order to distinguish between 128 and 256
     // memory forms of these instructions in Asm Parcer. They have the same
     // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
     // due to the same reason.
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v2f64x_info, OpNode,
                                "{1to2}", "{x}">, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i32x_info, v4f64x_info, OpNode,
                                "{1to4}", "{y}">, EVEX_V256;
   }
 }
 
 // Convert Double to Signed/Unsigned Quardword
 multiclass avx512_cvtpd2qq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f64_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasDQI, HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
                                EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
                                EVEX_V256;
   }
 }
 
 // Convert Double to Signed/Unsigned Quardword with truncation
 multiclass avx512_cvttpd2qq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f64_info, OpNode>,
-             avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f64_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasDQI, HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v2f64x_info, OpNode>,
                                EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f64x_info, OpNode>,
                                EVEX_V256;
   }
 }
 
 // Convert Signed/Unsigned Quardword to Double
 multiclass avx512_cvtqq2pd<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f64_info, v8i64_info, OpNode>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v8f64_info, v8i64_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasDQI, HasVLX] in {
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2f64x_info, v2i64x_info, OpNode>,
                                EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f64x_info, v4i64x_info, OpNode>,
                                EVEX_V256;
   }
 }
 
 // Convert Float to Signed/Unsigned Quardword
 multiclass avx512_cvtps2qq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v8i64_info, v8f32x_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasDQI, HasVLX] in {
     // Explicitly specified broadcast string, since we take only 2 elements
     // from v4f32x_info source
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
                                "{1to2}">, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
                                EVEX_V256;
   }
 }
 
 // Convert Float to Signed/Unsigned Quardword with truncation
 multiclass avx512_cvttps2qq<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8i64_info, v8f32x_info, OpNode>,
-             avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_sae<opc, OpcodeStr, v8i64_info, v8f32x_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasDQI, HasVLX] in {
     // Explicitly specified broadcast string, since we take only 2 elements
     // from v4f32x_info source
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v2i64x_info, v4f32x_info, OpNode,
                                "{1to2}">, EVEX_V128;
     defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4i64x_info, v4f32x_info, OpNode>,
                                EVEX_V256;
   }
 }
 
 // Convert Signed/Unsigned Quardword to Float
 multiclass avx512_cvtqq2ps<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode, SDNode OpNodeRnd> {
   let Predicates = [HasDQI] in {
     defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8i64_info, OpNode>,
-             avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
-                               OpNodeRnd>, EVEX_V512;
+                            EVEX_V512;
+    defm Z : avx512_vcvt_fp_rc<opc, OpcodeStr, v8f32x_info, v8i64_info,
+                               OpNodeRnd>;
   }
   let Predicates = [HasDQI, HasVLX] in {
     // we need "x"/"y" suffixes in order to distinguish between 128 and 256
     // memory forms of these instructions in Asm Parcer. They have the same
     // dest type - 'v4i32x_info'. We also specify the broadcast string explicitly
     // due to the same reason.
     defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v2i64x_info, OpNode,
                                "{1to2}", "{x}">, EVEX_V128;
defm rm : AVX512_maskable<0x13, MRMSrcMem, _dest, (outs _dest.RC:$dst), (ins x86memop:$src),
                     (X86cvtph2ps (_src.VT (bitconvert (ld_frag addr:$src))),
                                      (i32 FROUND_CURRENT))>, T8PD;
 }
 
 multiclass avx512_cvtph2ps_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
   defm rb : AVX512_maskable<0x13, MRMSrcReg, _dest ,(outs _dest.RC:$dst), (ins _src.RC:$src),
                     "vcvtph2ps", "{sae}, $src", "$src, {sae}",
                    (X86cvtph2ps (_src.VT _src.RC:$src),
-                                                (i32 FROUND_NO_EXC))>, T8PD, EVEX_B;
+                                                (i32 FROUND_NO_EXC))>, T8PD, VEX_LIG, EVEX_B;
 
 }
 
 let Predicates = [HasAVX512] in {
   defm VCVTPH2PSZ : avx512_cvtph2ps<v16f32_info, v16i16x_info, f256mem, loadv4i64>,
-                    avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
                     EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
+  defm VCVTPH2PSZ : avx512_cvtph2ps_sae<v16f32_info, v16i16x_info>,
+                    EVEX, EVEX_CD8<32, CD8VH>;
   let Predicates = [HasVLX] in {
     defm VCVTPH2PSZ256 : avx512_cvtph2ps<v8f32x_info, v8i16x_info, f128mem,
                          loadv2i64>,EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
     defm VCVTPH2PSZ128 : avx512_cvtph2ps<v4f32x_info, v8i16x_info, f64mem,
                          loadv2i64>, EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
   }
 }
 
def mrk : AVX512AIi8<0x1D, MRMDestMem, (outs),
               []>, EVEX_K;
 }
 multiclass avx512_cvtps2ph_sae<X86VectorVTInfo _dest, X86VectorVTInfo _src> {
   let hasSideEffects = 0 in
   defm rb : AVX512_maskable_in_asm<0x1D, MRMDestReg, _dest,
                    (outs _dest.RC:$dst),
                    (ins _src.RC:$src1, i32u8imm:$src2),
                    "vcvtps2ph", "$src2, {sae}, $src1", "$src1, {sae}, $src2",
-                   []>, EVEX_B, AVX512AIi8Base;
+                   []>, VEX_LIG, EVEX_B, AVX512AIi8Base;
 }
 let Predicates = [HasAVX512] in {
   defm VCVTPS2PHZ : avx512_cvtps2ph<v16i16x_info, v16f32_info, f256mem>,
-                    avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
                       EVEX, EVEX_V512, EVEX_CD8<32, CD8VH>;
+  defm VCVTPS2PHZ : avx512_cvtps2ph_sae<v16i16x_info, v16f32_info>,
+                      EVEX, EVEX_CD8<32, CD8VH>;
   let Predicates = [HasVLX] in {
     defm VCVTPS2PHZ256 : avx512_cvtps2ph<v8i16x_info, v8f32x_info, f128mem>,
                         EVEX, EVEX_V256, EVEX_CD8<32, CD8VH>;
     defm VCVTPS2PHZ128 : avx512_cvtps2ph<v8i16x_info, v4f32x_info, f128mem>,
                         EVEX, EVEX_V128, EVEX_CD8<32, CD8VH>;
   }
 }
 
defm mb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
                                   (X86VBroadcast (_.ScalarLdFrag addr:$src))),
                                  (i32 FROUND_CURRENT))>, EVEX_B;
 }
 multiclass avx512_fp28_p_round<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
                          SDNode OpNode> {
   defm rb : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                         (ins _.RC:$src), OpcodeStr,
                         "{sae}, $src", "$src, {sae}",
-                        (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>, EVEX_B;
+                        (OpNode (_.VT _.RC:$src), (i32 FROUND_NO_EXC))>,
+                        VEX_LIG, EVEX_B;
 }
 
 multiclass  avx512_eri<bits<8> opc, string OpcodeStr, SDNode OpNode> {
    defm PS : avx512_fp28_p<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
-             avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
              T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
+   defm PS : avx512_fp28_p_round<opc, OpcodeStr#"ps", v16f32_info, OpNode>,
+             T8PD, EVEX_CD8<32, CD8VF>;
    defm PD : avx512_fp28_p<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
-             avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
              T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
+   defm PD : avx512_fp28_p_round<opc, OpcodeStr#"pd", v8f64_info, OpNode>,
+             T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
 }
 
 multiclass avx512_fp_unaryop_packed<bits<8> opc, string OpcodeStr,
                                   SDNode OpNode> {
   // Define only if AVX512VL feature is present.
   let Predicates = [HasVLX] in {
     defm PSZ128 : avx512_fp28_p<opc, OpcodeStr#"ps", v4f32x_info, OpNode>,
                                      EVEX_V128, T8PD, EVEX_CD8<32, CD8VF>;

 defm VGETEXP   : avx512_eri<0x42, "vgetexp", X86fgetexpRnd>,
                  avx512_fp_unaryop_packed<0x42, "vgetexp", X86fgetexpRnd> , EVEX;
 
 multiclass avx512_sqrt_packed_round<bits<8> opc, string OpcodeStr,
                               SDNode OpNodeRnd, X86VectorVTInfo _>{
   defm rb: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _.RC:$src, AVX512RC:$rc), OpcodeStr, "$rc, $src", "$src, $rc",
                          (_.VT (OpNodeRnd _.RC:$src, (i32 imm:$rc)))>,
-                         EVEX, EVEX_B, EVEX_RC;
+                         VEX_LIG, EVEX, EVEX_B, EVEX_RC;
 }
 
 multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr,
                               SDNode OpNode, X86VectorVTInfo _>{
   defm r: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _.RC:$src), OpcodeStr, "$src", "$src",
                          (_.FloatVT (OpNode _.RC:$src))>, EVEX;
   defm m: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
defm PDZ256 : avx512_sqrt_packed<opc, !strconcat(OpcodeStr, "pd"),
                                      OpNode, v4f64x_info>,
                                      EVEX_V256, VEX_W, PD, EVEX_CD8<64, CD8VF>;
   }
 }
 
 multiclass avx512_sqrt_packed_all_round<bits<8> opc, string OpcodeStr,
                                           SDNode OpNodeRnd> {
   defm PSZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "ps"), OpNodeRnd,
-                                v16f32_info>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
+                                v16f32_info>, PS, EVEX_CD8<32, CD8VF>;
   defm PDZ : avx512_sqrt_packed_round<opc, !strconcat(OpcodeStr, "pd"), OpNodeRnd,
-                                v8f64_info>, EVEX_V512, VEX_W, PD, EVEX_CD8<64, CD8VF>;
+                                v8f64_info>, VEX_W, PD, EVEX_CD8<64, CD8VF>;
 }
 
 multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
                               string SUFF, SDNode OpNode, SDNode OpNodeRnd> {
 
   defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                          (ins _.RC:$src1, _.RC:$src2), OpcodeStr,
                          "$src2, $src1", "$src1, $src2",
multiclass avx512_unary_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
                                              SDNode OpNode, X86VectorVTInfo _>{
   let ExeDomain = _.ExeDomain in
   defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                       (ins _.RC:$src1, i32u8imm:$src2),
                       OpcodeStr##_.Suffix, "$src2, {sae}, $src1",
                       "$src1, {sae}, $src2",
                       (OpNode (_.VT _.RC:$src1),
                               (i32 imm:$src2),
-                              (i32 FROUND_NO_EXC))>, EVEX_B;
+                              (i32 FROUND_NO_EXC))>, VEX_LIG, EVEX_B;
 }
 
 multiclass avx512_common_unary_fp_sae_packed_imm<string OpcodeStr,
             AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
   let Predicates = [prd] in {
     defm Z    : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
-                avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
                                   EVEX_V512;
+    defm Z    : avx512_unary_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>;
   }
   let Predicates = [prd, HasVLX] in {
     defm Z128 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
                                   EVEX_V128;
     defm Z256 : avx512_unary_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
                                   EVEX_V256;
   }
 }
multiclass avx512_fp_sae_packed_imm<bits<8> opc, string OpcodeStr,
   let ExeDomain = _.ExeDomain in
   defm rrib : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
                       (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
                       OpcodeStr, "$src3, {sae}, $src2, $src1",
                       "$src1, $src2, {sae}, $src3",
                       (OpNode (_.VT _.RC:$src1),
                               (_.VT _.RC:$src2),
                               (i32 imm:$src3),
-                              (i32 FROUND_NO_EXC))>, EVEX_B;
+                              (i32 FROUND_NO_EXC))>, VEX_LIG, EVEX_B;
 }
 //handle scalar instruction  reg_vec1 = op(reg_vec2,reg_vec3,imm),{sae}
 multiclass avx512_fp_sae_scalar_imm<bits<8> opc, string OpcodeStr,
                                              SDNode OpNode, X86VectorVTInfo _> {
   defm NAME#rrib : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
                       (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3),
                       OpcodeStr, "$src3, {sae}, $src2, $src1",
                       "$src1, $src2, {sae}, $src3",
                       (OpNode (_.VT _.RC:$src1),
                               (_.VT _.RC:$src2),
                               (i32 imm:$src3),
                               (i32 FROUND_NO_EXC))>, EVEX_B;
 }
 
 multiclass avx512_common_fp_sae_packed_imm<string OpcodeStr,
             AVX512VLVectorVTInfo _, bits<8> opc, SDNode OpNode, Predicate prd>{
   let Predicates = [prd] in {
     defm Z    : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
-                avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>,
                                   EVEX_V512;
-
+    defm Z    : avx512_fp_sae_packed_imm<opc, OpcodeStr, OpNode, _.info512>;
   }
   let Predicates = [prd, HasVLX] in {
     defm Z128 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info128>,
                                   EVEX_V128;
     defm Z256 : avx512_fp_packed_imm<opc, OpcodeStr, OpNode, _.info256>,
                                   EVEX_V256;
   }
 }
let Constraints = "$src1 = $dst", ExeDomain = _.ExeDomain in {
   defm rrib : AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
                       (ins _.RC:$src2, _.RC:$src3, i32u8imm:$src4),
                       OpcodeStr##_.Suffix, "$src4, {sae}, $src3, $src2",
                       "$src2, $src3, {sae}, $src4",
                       (OpNode (_.VT _.RC:$src1),
                                 (_.VT _.RC:$src2),
                                 (_.IntVT _.RC:$src3),
                                 (i32 imm:$src4),
-                                (i32 FROUND_NO_EXC))>, EVEX_B;
+                                (i32 FROUND_NO_EXC))>, VEX_LIG, EVEX_B;
   }
 }
 
 multiclass avx512_fixupimm_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
                                   X86VectorVTInfo _, X86VectorVTInfo _src3VT> {
   let Constraints = "$src1 = $dst" , Predicates = [HasAVX512],
       ExeDomain = _.ExeDomain in {
     defm rri : AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
defm rmi : AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
                              (i32 imm:$src4),
                              (i32 FROUND_CURRENT))>;
   }
 }
 
 multiclass avx512_fixupimm_packed_all<AVX512VLVectorVTInfo _Vec>{
   let Predicates = [HasAVX512] in
     defm Z    : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info512>,
-                avx512_fixupimm_packed_sae<0x54, "vfixupimm", X86VFixupimm, _Vec.info512>,
                                   AVX512AIi8Base, EVEX_4V, EVEX_V512;
+    defm Z    : avx512_fixupimm_packed_sae<0x54, "vfixupimm", X86VFixupimm, _Vec.info512>,
+                                  AVX512AIi8Base, EVEX_4V;
   let Predicates = [HasAVX512, HasVLX] in {
     defm Z128 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info128>,
                                   AVX512AIi8Base, EVEX_4V, EVEX_V128;
     defm Z256 : avx512_fixupimm_packed<0x54, "vfixupimm", X86VFixupimm, _Vec.info256>,
                                   AVX512AIi8Base, EVEX_4V, EVEX_V256;
   }
 }
 

test/MC/Disassembler/X86/avx-512.txt

 0x62 0xd3 0x35 0x40 0x1f 0xea 0x6
 
 # CHECK: vpcmpd $7, %zmm10, %zmm25, %k5
 0x62 0xd3 0x35 0x40 0x1f 0xea 0x7
 
 # CHECK: vpcmpd $8, %zmm10, %zmm25, %k5
 0x62 0xd3 0x35 0x40 0x1f 0xea 0x8
 
+#####################################################
+#                  SAE ATTRIBUTE                    #
+#####################################################
+
+# CHECK: vcomisd {sae}, %xmm2, %xmm1
+0x62 0xf1 0xfd 0x18 0x2f 0xca
+
+# Same as above but ignore EVEX L'L bits.
+# CHECK: vcomisd {sae}, %xmm2, %xmm1
+0x62 0xf1 0xfd 0x78 0x2f 0xca
+
+# Ignore L'L bits  without {sae} bit set.
+# CHECK: vcomisd %xmm2, %xmm1
+0x62 0xf1 0xfd 0x68 0x2f 0xca
+
+# CHECK: vminpd  {sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0xf5 0x10 0x5d 0xda
+
+# Ignore EVEX L'L bits.
+# CHECK: vminpd  {sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0xf5 0x30 0x5d 0xda
+
+# Ignore EVEX L'L bits.
+# CHECK: vminpd  {sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0xf5 0x50 0x5d 0xda
+
+# Ignore EVEX L'L bits.
+# CHECK: vminpd  {sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0xf5 0x70 0x5d 0xda
+
+# Without {sae} L'L modifies size.
+# CHECK: vminpd  %ymm2, %ymm17, %ymm19
+0x62 0xe1 0xf5 0x20 0x5d 0xda
+
+# CHECK: vcmppd $127, {sae}, %zmm27, %zmm11, %k4
+0x62 0x91 0xa5 0x18 0xc2 0xe3 0x7f
+
 # CHECK: vcmppd $127, {sae}, %zmm27, %zmm11, %k4
 0x62 0x91 0xa5 0x58 0xc2 0xe3 0x7f
+
+# CHEC: vrsqrt28pd      {sae}, %zmm2, %zmm17
+0x62 0xe2 0xfd 0x18 0xcc 0xca
+
+#####################################################
+#                 ROUNDING CONTROL                  #
+#####################################################
+
+# Verify all rounding modes work.
+
+# CHECK: vaddps  {rn-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0x74 0x10 0x58 0xda
+
+# CHECK: vaddps  {rd-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0x74 0x30 0x58 0xda
+
+# CHECK: vaddps  {ru-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0x74 0x50 0x58 0xda
+
+# CHECK: vaddps  {rz-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe1 0x74 0x70 0x58 0xda
+
+# Without rounding control L'L control vector size.
+# CHECK: vaddps  %ymm2, %ymm17, %ymm19
+0x62 0xe1 0x74 0x20 0x58 0xda
+
+# CHECK: vmulss  {rn-sae}, %xmm2, %xmm17, %xmm19
+0x62 0xe1 0x76 0x10 0x59 0xda
+
+# CHECK: vmulss  {rd-sae}, %xmm2, %xmm17, %xmm19
+0x62 0xe1 0x76 0x30 0x59 0xda
+
+# CHECK: vmulss  {ru-sae}, %xmm2, %xmm17, %xmm19
+0x62 0xe1 0x76 0x50 0x59 0xda
+
+# CHECK: vmulss  {rz-sae}, %xmm2, %xmm17, %xmm19
+0x62 0xe1 0x76 0x70 0x59 0xda
+
+# CHECK: vscalefpd       {rn-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe2 0xf5 0x10 0x2c 0xda
+
+# CHECK: vscalefpd       {rd-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe2 0xf5 0x30 0x2c 0xda
+
+# CHECK: vscalefpd       {ru-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe2 0xf5 0x50 0x2c 0xda
+
+# CHECK: vscalefpd       {rz-sae}, %zmm2, %zmm17, %zmm19
+0x62 0xe2 0xf5 0x70 0x2c 0xda
+
+# Without rounding control L'L control vector size.
+# CHECK: vscalefpd       %ymm2, %ymm17, %ymm19
+0x62 0xe2 0xf5 0x20 0x2c 0xda
+
+# CHECK: vcvtqq2ps       {rd-sae}, %zmm2, %ymm17
+0x62 0xe1 0xfc 0x38 0x5b 0xca
+
+# CHECK: vsqrtpd {rd-sae}, %zmm2, %zmm17
+0x62 0xe1 0xfd 0x38 0x51 0xca
+
+# CHECK: vsqrtpd %ymm2, %ymm17
+0x62 0xe1 0xfd 0x28 0x51 0xca

utils/TableGen/X86DisassemblerTables.cpp

static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
   default:
     llvm_unreachable("Unhandled encoding");
 #define ENUM_ENTRY(i, d) case i: return #i;
   ENCODINGS
 #undef ENUM_ENTRY
   }
 }
 
+/// Return instruction context combined with EVEX_L.
+static inline InstructionContext combineEVEX_L(InstructionContext insnContext) {
+  switch (insnContext) {
+  default:
+    return insnContext;
+  case IC_EVEX:               return IC_EVEX_L;
+  case IC_EVEX_W:             return IC_EVEX_L_W;
+  case IC_EVEX_W_XS:          return IC_EVEX_L_W_XS;
+  case IC_EVEX_W_XD:          return IC_EVEX_L_W_XD;
+  case IC_EVEX_W_OPSIZE:      return IC_EVEX_L_W_OPSIZE;
+  case IC_EVEX_K_B:           return IC_EVEX_L_K_B;
+  case IC_EVEX_KZ_B:          return IC_EVEX_L_KZ_B;
+  case IC_EVEX_B:             return IC_EVEX_L_B;
+  case IC_EVEX_XS:            return IC_EVEX_L_XS;
+  case IC_EVEX_XD:            return IC_EVEX_L_XD;
+  case IC_EVEX_OPSIZE:        return IC_EVEX_L_OPSIZE;
+  case IC_EVEX_W_XS_K:        return IC_EVEX_L_W_XS_K;
+  case IC_EVEX_W_XD_K:        return IC_EVEX_L_W_XD_K;
+  case IC_EVEX_W_XS_KZ:       return IC_EVEX_L_W_XS_KZ;
+  case IC_EVEX_W_XD_KZ:       return IC_EVEX_L_W_XD_KZ;
+  case IC_EVEX_W_OPSIZE_B:    return IC_EVEX_L_W_OPSIZE_B;
+  case IC_EVEX_K:             return IC_EVEX_L_K;
+  case IC_EVEX_XS_K:          return IC_EVEX_L_XS_K;
+  case IC_EVEX_XD_K:          return IC_EVEX_L_XD_K;
+  case IC_EVEX_XD_B:          return IC_EVEX_L_XD_B;
+  case IC_EVEX_XD_K_B:        return IC_EVEX_L_XD_K_B;
+  case IC_EVEX_OPSIZE_K:      return IC_EVEX_L_OPSIZE_K;
+  case IC_EVEX_OPSIZE_B:      return IC_EVEX_L_OPSIZE_B;
+  case IC_EVEX_OPSIZE_K_B:    return IC_EVEX_L_OPSIZE_K_B;
+  case IC_EVEX_KZ:            return IC_EVEX_L_KZ;
+  case IC_EVEX_XS_KZ:         return IC_EVEX_L_XS_KZ;
+  case IC_EVEX_XS_B:          return IC_EVEX_L_XS_B;
+  case IC_EVEX_XS_K_B:        return IC_EVEX_L_XS_K_B;
+  case IC_EVEX_XS_KZ_B:       return IC_EVEX_L_XS_KZ_B;
+  case IC_EVEX_XD_KZ:         return IC_EVEX_L_XD_KZ;
+  case IC_EVEX_XD_KZ_B:       return IC_EVEX_L_XD_KZ_B;
+  case IC_EVEX_OPSIZE_KZ:     return IC_EVEX_L_OPSIZE_KZ;
+  case IC_EVEX_OPSIZE_KZ_B:   return IC_EVEX_L_OPSIZE_KZ_B;
+  case IC_EVEX_W_K:           return IC_EVEX_L_W_K;
+  case IC_EVEX_W_B:           return IC_EVEX_L_W_B;
+  case IC_EVEX_W_K_B:         return IC_EVEX_L_W_K_B;
+  case IC_EVEX_W_XS_B:        return IC_EVEX_L_W_XS_B;
+  case IC_EVEX_W_XS_K_B:      return IC_EVEX_L_W_XS_K_B;
+  case IC_EVEX_W_XS_KZ_B:     return IC_EVEX_L_W_XS_KZ_B;
+  case IC_EVEX_W_OPSIZE_K:    return IC_EVEX_L_W_OPSIZE_K;
+  case IC_EVEX_W_OPSIZE_K_B:  return IC_EVEX_L_W_OPSIZE_K_B;
+  case IC_EVEX_W_KZ:          return IC_EVEX_L_W_KZ;
+  case IC_EVEX_W_KZ_B:        return IC_EVEX_L_W_KZ_B;
+  case IC_EVEX_W_XD_B:        return IC_EVEX_L_W_XD_B;
+  case IC_EVEX_W_XD_K_B:      return IC_EVEX_L_W_XD_K_B;
+  case IC_EVEX_W_XD_KZ_B:     return IC_EVEX_L_W_XD_KZ_B;
+  case IC_EVEX_W_OPSIZE_KZ:   return IC_EVEX_L_W_OPSIZE_KZ;
+  case IC_EVEX_W_OPSIZE_KZ_B: return IC_EVEX_L_W_OPSIZE_KZ_B;
+  }
+}
+
+/// Return instruction context combined with EVEX_L2.
+static inline InstructionContext combineEVEX_L2(InstructionContext insnContext){
+  switch (insnContext) {
+  default:
+    return insnContext;
+  case IC_EVEX:               return IC_EVEX_L2;
+  case IC_EVEX_W:             return IC_EVEX_L2_W;
+  case IC_EVEX_W_XS:          return IC_EVEX_L2_W_XS;
+  case IC_EVEX_W_XD:          return IC_EVEX_L2_W_XD;
+  case IC_EVEX_W_OPSIZE:      return IC_EVEX_L2_W_OPSIZE;
+  case IC_EVEX_K_B:           return IC_EVEX_L2_K_B;
+  case IC_EVEX_KZ_B:          return IC_EVEX_L2_KZ_B;
+  case IC_EVEX_B:             return IC_EVEX_L2_B;
+  case IC_EVEX_XS:            return IC_EVEX_L2_XS;
+  case IC_EVEX_XD:            return IC_EVEX_L2_XD;
+  case IC_EVEX_OPSIZE:        return IC_EVEX_L2_OPSIZE;
+  case IC_EVEX_W_XS_K:        return IC_EVEX_L2_W_XS_K;
+  case IC_EVEX_W_XD_K:        return IC_EVEX_L2_W_XD_K;
+  case IC_EVEX_W_XS_KZ:       return IC_EVEX_L2_W_XS_KZ;
+  case IC_EVEX_W_XD_KZ:       return IC_EVEX_L2_W_XD_KZ;
+  case IC_EVEX_W_OPSIZE_B:    return IC_EVEX_L2_W_OPSIZE_B;
+  case IC_EVEX_K:             return IC_EVEX_L2_K;
+  case IC_EVEX_XS_K:          return IC_EVEX_L2_XS_K;
+  case IC_EVEX_XD_K:          return IC_EVEX_L2_XD_K;
+  case IC_EVEX_XD_B:          return IC_EVEX_L2_XD_B;
+  case IC_EVEX_XD_K_B:        return IC_EVEX_L2_XD_K_B;
+  case IC_EVEX_OPSIZE_K:      return IC_EVEX_L2_OPSIZE_K;
+  case IC_EVEX_OPSIZE_B:      return IC_EVEX_L2_OPSIZE_B;
+  case IC_EVEX_OPSIZE_K_B:    return IC_EVEX_L2_OPSIZE_K_B;
+  case IC_EVEX_KZ:            return IC_EVEX_L2_KZ;
+  case IC_EVEX_XS_KZ:         return IC_EVEX_L2_XS_KZ;
+  case IC_EVEX_XS_B:          return IC_EVEX_L2_XS_B;
+  case IC_EVEX_XS_K_B:        return IC_EVEX_L2_XS_K_B;
+  case IC_EVEX_XS_KZ_B:       return IC_EVEX_L2_XS_KZ_B;
+  case IC_EVEX_XD_KZ:         return IC_EVEX_L2_XD_KZ;
+  case IC_EVEX_XD_KZ_B:       return IC_EVEX_L2_XD_KZ_B;
+  case IC_EVEX_OPSIZE_KZ:     return IC_EVEX_L2_OPSIZE_KZ;
+  case IC_EVEX_OPSIZE_KZ_B:   return IC_EVEX_L2_OPSIZE_KZ_B;
+  case IC_EVEX_W_K:           return IC_EVEX_L2_W_K;
+  case IC_EVEX_W_B:           return IC_EVEX_L2_W_B;
+  case IC_EVEX_W_K_B:         return IC_EVEX_L2_W_K_B;
+  case IC_EVEX_W_XS_B:        return IC_EVEX_L2_W_XS_B;
+  case IC_EVEX_W_XS_K_B:      return IC_EVEX_L2_W_XS_K_B;
+  case IC_EVEX_W_XS_KZ_B:     return IC_EVEX_L2_W_XS_KZ_B;
+  case IC_EVEX_W_OPSIZE_K:    return IC_EVEX_L2_W_OPSIZE_K;
+  case IC_EVEX_W_OPSIZE_K_B:  return IC_EVEX_L2_W_OPSIZE_K_B;
+  case IC_EVEX_W_KZ:          return IC_EVEX_L2_W_KZ;
+  case IC_EVEX_W_KZ_B:        return IC_EVEX_L2_W_KZ_B;
+  case IC_EVEX_W_XD_B:        return IC_EVEX_L2_W_XD_B;
+  case IC_EVEX_W_XD_K_B:      return IC_EVEX_L2_W_XD_K_B;
+  case IC_EVEX_W_XD_KZ_B:     return IC_EVEX_L2_W_XD_KZ_B;
+  case IC_EVEX_W_OPSIZE_KZ:   return IC_EVEX_L2_W_OPSIZE_KZ;
+  case IC_EVEX_W_OPSIZE_KZ_B: return IC_EVEX_L2_W_OPSIZE_KZ_B;
+  }
+}
+
 /// inheritsFrom - Indicates whether all instructions in one class also belong
 ///   to another class.
 ///
 /// @param child  - The class that may be the subset
 /// @param parent - The class that may be the superset
 /// @return       - True if child is a subset of parent, false otherwise.
 static inline bool inheritsFrom(InstructionContext child,
                                 InstructionContext parent,
case IC_VEX_L_OPSIZE:
     return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
   case IC_VEX_L_W:
   case IC_VEX_L_W_XS:
   case IC_VEX_L_W_XD:
   case IC_VEX_L_W_OPSIZE:
     return false;
   case IC_EVEX:
     return inheritsFrom(child, IC_EVEX_W) ||
-           inheritsFrom(child, IC_EVEX_L_W);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_XS:
     return inheritsFrom(child, IC_EVEX_W_XS) ||
-           inheritsFrom(child, IC_EVEX_L_W_XS);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_XD:
     return inheritsFrom(child, IC_EVEX_W_XD) ||
-           inheritsFrom(child, IC_EVEX_L_W_XD);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_OPSIZE:
     return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
-           inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_B:
-    return false;
   case IC_EVEX_W:
   case IC_EVEX_W_XS:
   case IC_EVEX_W_XD:
   case IC_EVEX_W_OPSIZE:
-    return false;
+    return VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                       inheritsFrom(child, combineEVEX_L2(parent)));
   case IC_EVEX_L:
   case IC_EVEX_L_K_B:
   case IC_EVEX_L_KZ_B:
   case IC_EVEX_L_B:
   case IC_EVEX_L_XS:
   case IC_EVEX_L_XD:
   case IC_EVEX_L_OPSIZE:
     return false;
case IC_EVEX_L2_OPSIZE:
     return false;
   case IC_EVEX_L2_W:
   case IC_EVEX_L2_W_XS:
   case IC_EVEX_L2_W_XD:
   case IC_EVEX_L2_W_OPSIZE:
     return false;
   case IC_EVEX_K:
     return inheritsFrom(child, IC_EVEX_W_K) ||
-           inheritsFrom(child, IC_EVEX_L_W_K);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_XS_K:
   case IC_EVEX_XS_K_B:
   case IC_EVEX_XS_KZ_B:
     return inheritsFrom(child, IC_EVEX_W_XS_K) ||
-           inheritsFrom(child, IC_EVEX_L_W_XS_K);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_XD_K:
   case IC_EVEX_XD_K_B:
   case IC_EVEX_XD_KZ_B:
     return inheritsFrom(child, IC_EVEX_W_XD_K) ||
-           inheritsFrom(child, IC_EVEX_L_W_XD_K);
-  case IC_EVEX_XS_B:
-  case IC_EVEX_XD_B:
-  case IC_EVEX_K_B:
-  case IC_EVEX_KZ:
-    return false;
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_XS_KZ:
     return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
-           inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
   case IC_EVEX_XD_KZ:
     return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
-           inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
+           (VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                        inheritsFrom(child, combineEVEX_L2(parent))));
+  case IC_EVEX_XS_B:
+  case IC_EVEX_XD_B:
+  case IC_EVEX_K_B:
+  case IC_EVEX_KZ:
   case IC_EVEX_KZ_B:
+
   case IC_EVEX_OPSIZE_K:
   case IC_EVEX_OPSIZE_B:
   case IC_EVEX_OPSIZE_K_B:
   case IC_EVEX_OPSIZE_KZ:
   case IC_EVEX_OPSIZE_KZ_B:
-    return false;
+
   case IC_EVEX_W_K:
   case IC_EVEX_W_B:
   case IC_EVEX_W_K_B:
   case IC_EVEX_W_KZ_B:
   case IC_EVEX_W_XS_K:
   case IC_EVEX_W_XD_K:
   case IC_EVEX_W_OPSIZE_K:
   case IC_EVEX_W_OPSIZE_B:
   case IC_EVEX_W_OPSIZE_K_B:
-    return false;
-  case IC_EVEX_L_K:
-  case IC_EVEX_L_XS_K:
-  case IC_EVEX_L_XD_K:
-  case IC_EVEX_L_XD_B:
-  case IC_EVEX_L_XD_K_B:
-  case IC_EVEX_L_OPSIZE_K:
-  case IC_EVEX_L_OPSIZE_B:
-  case IC_EVEX_L_OPSIZE_K_B:
-    return false;
+
   case IC_EVEX_W_KZ:
   case IC_EVEX_W_XS_KZ:
   case IC_EVEX_W_XD_KZ:
   case IC_EVEX_W_XS_B:
   case IC_EVEX_W_XD_B:
   case IC_EVEX_W_XS_K_B:
   case IC_EVEX_W_XD_K_B:
   case IC_EVEX_W_XS_KZ_B:
   case IC_EVEX_W_XD_KZ_B:
   case IC_EVEX_W_OPSIZE_KZ:
   case IC_EVEX_W_OPSIZE_KZ_B:
+    return VEX_LIG && (inheritsFrom(child, combineEVEX_L(parent)) ||
+                       inheritsFrom(child, combineEVEX_L2(parent)));
+  case IC_EVEX_L_K:
+  case IC_EVEX_L_XS_K:
+  case IC_EVEX_L_XD_K:
+  case IC_EVEX_L_XD_B:
+  case IC_EVEX_L_XD_K_B:
+  case IC_EVEX_L_OPSIZE_K:
+  case IC_EVEX_L_OPSIZE_B:
+  case IC_EVEX_L_OPSIZE_K_B:
     return false;
   case IC_EVEX_L_KZ:
   case IC_EVEX_L_XS_KZ:
   case IC_EVEX_L_XS_B:
   case IC_EVEX_L_XS_K_B:
   case IC_EVEX_L_XS_KZ_B:
   case IC_EVEX_L_XD_KZ:
   case IC_EVEX_L_XD_KZ_B:

utils/TableGen/X86RecognizableInstr.cpp

OperandType RecognizableInstr::typeFromString(const std::string &s,
   TYPE("i512mem",             TYPE_M512)
   TYPE("i64i32imm_pcrel",     TYPE_REL64)
   TYPE("i16imm_pcrel",        TYPE_REL16)
   TYPE("i32imm_pcrel",        TYPE_REL32)
   TYPE("SSECC",               TYPE_IMM3)
   TYPE("XOPCC",               TYPE_IMM3)
   TYPE("AVXCC",               TYPE_IMM5)
   TYPE("AVX512ICC",           TYPE_AVX512ICC)
-  TYPE("AVX512RC",            TYPE_IMM32)
+  TYPE("AVX512RC",            TYPE_IMM8)
   TYPE("brtarget32",          TYPE_RELv)
   TYPE("brtarget16",          TYPE_RELv)
   TYPE("brtarget8",           TYPE_REL8)
   TYPE("f80mem",              TYPE_M80FP)
   TYPE("lea64_32mem",         TYPE_LEA)
   TYPE("lea64mem",            TYPE_LEA)
   TYPE("VR64",                TYPE_MM64)
   TYPE("i64imm",              TYPE_IMMv)
if(OpSize != X86Local::OpSize16) {
     // immediate encoding is special.
     ENCODING("i16imm",        ENCODING_IW)
   }
   ENCODING("i32i8imm",        ENCODING_IB)
   ENCODING("SSECC",           ENCODING_IB)
   ENCODING("XOPCC",           ENCODING_IB)
   ENCODING("AVXCC",           ENCODING_IB)
   ENCODING("AVX512ICC",       ENCODING_IB)
-  ENCODING("AVX512RC",        ENCODING_IB)
+  ENCODING("AVX512RC",        ENCODING_Irc)
   ENCODING("i16imm",          ENCODING_Iv)
   ENCODING("i16i8imm",        ENCODING_IB)
   ENCODING("i32imm",          ENCODING_Iv)
   ENCODING("i64i32imm",       ENCODING_ID)
   ENCODING("i64i8imm",        ENCODING_IB)
   ENCODING("i8imm",           ENCODING_IB)
   ENCODING("u8imm",           ENCODING_IB)
   ENCODING("i32u8imm",        ENCODING_IB)