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Differential D25546

[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations
ClosedPublic

Authored by kzhuravl on Oct 12 2016, 9:58 PM.

Details

Reviewers
tony-tye
• tstellarAMD
Commits
rGee68fdadfe96: [Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations
rL284191: [Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations
Summary

Added relocation names:

  • R_AMDGPU_GOTPCREL32_LO
  • R_AMDGPU_GOTPCREL32_HI
  • R_AMDGPU_REL32_LO
  • R_AMDGPU_REL32_HI

AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above.

Diff Detail

Event Timeline

kzhuravl updated this revision to Diff 74474.Oct 12 2016, 9:58 PM
kzhuravl retitled this revision from to [Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations.
kzhuravl updated this object.
kzhuravl added reviewers: • tstellarAMD, tony-tye.
kzhuravl added a subscriber: llvm-commits.
Herald edited edge metadata. · View Herald TranscriptOct 12 2016, 9:58 PM
Herald added subscribers: yaxunl, nhaehnle, wdng. · View Herald Transcript
kzhuravl added subscribers: b-sumner, cfang.Oct 13 2016, 8:22 AM
kzhuravl added child revisions: D25548: [AMDGPU] Add 32-bit lo/hi got and pc relative variant kinds and emit appropriate relocations, D25563: [ELF/AMDGPU]: Add support for new relocations.Oct 13 2016, 8:27 AM
• tstellarAMD accepted this revision.Oct 13 2016, 2:36 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Oct 13 2016, 2:36 PM
Closed by commit rL284191: [Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations (authored by kzhuravl). · Explain WhyOct 13 2016, 9:12 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
docs/
28 lines
include/
llvm/
Support/
ELFRelocs/
20 lines
test/
Object/
AMDGPU/
60 lines

Diff 74474

docs/CodeGenerator.rst

Show First 20 Lines • Show All 2,676 Lines • ▼ Show 20 Lines
* **P** --- Represents the place (section offset or address) of the storage unit * **P** --- Represents the place (section offset or address) of the storage unit
being relocated (computed using ``r_offset``) being relocated (computed using ``r_offset``)
* **S** --- Represents the value of the symbol whose index resides in the * **S** --- Represents the value of the symbol whose index resides in the
relocation entry relocation entry
AMDGPU Backend generates *Elf64_Rela* relocation records with the following AMDGPU Backend generates *Elf64_Rela* relocation records with the following
supported relocation types: supported relocation types:
===================== ===== ========== ==================== ========================== ===== ========== ==============================
Relocation type Value Field Calculation Relocation type Value Field Calculation
===================== ===== ========== ==================== ========================== ===== ========== ==============================
``R_AMDGPU_NONE`` 0 ``none`` ``none`` ``R_AMDGPU_NONE`` 0 ``none`` ``none``
``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF ``R_AMDGPU_ABS32_LO`` 1 ``word32`` (S + A) & 0xFFFFFFFF
``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32 ``R_AMDGPU_ABS32_HI`` 2 ``word32`` (S + A) >> 32
``R_AMDGPU_ABS64`` 3 ``word64`` S + A ``R_AMDGPU_ABS64`` 3 ``word64`` S + A
``R_AMDGPU_REL32`` 4 ``word32`` S + A - P ``R_AMDGPU_REL32`` 4 ``word32`` S + A - P
``R_AMDGPU_REL64`` 5 ``word64`` S + A - P ``R_AMDGPU_REL64`` 5 ``word64`` S + A - P
``R_AMDGPU_ABS32`` 6 ``word32`` S + A ``R_AMDGPU_ABS32`` 6 ``word32`` S + A
``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P ``R_AMDGPU_GOTPCREL`` 7 ``word32`` G + GOT + A - P
===================== ===== ========== ==================== ``R_AMDGPU_GOTPCREL32_LO`` 8 ``word32`` (G + GOT + A - P) & 0xFFFFFFFF
``R_AMDGPU_GOTPCREL32_HI`` 9 ``word32`` (G + GOT + A - P) >> 32
``R_AMDGPU_REL32_LO`` 10 ``word32`` (S + A - P) & 0xFFFFFFFF
``R_AMDGPU_REL32_HI`` 11 ``word32`` (S + A - P) >> 32
========================== ===== ========== ==============================

include/llvm/Support/ELFRelocs/AMDGPU.def

#ifndef ELF_RELOC #ifndef ELF_RELOC
#error "ELF_RELOC must be defined" #error "ELF_RELOC must be defined"
#endif #endif
ELF_RELOC(R_AMDGPU_NONE, 0) ELF_RELOC(R_AMDGPU_NONE, 0)
ELF_RELOC(R_AMDGPU_ABS32_LO, 1) ELF_RELOC(R_AMDGPU_ABS32_LO, 1)
ELF_RELOC(R_AMDGPU_ABS32_HI, 2) ELF_RELOC(R_AMDGPU_ABS32_HI, 2)
ELF_RELOC(R_AMDGPU_ABS64, 3) ELF_RELOC(R_AMDGPU_ABS64, 3)
ELF_RELOC(R_AMDGPU_REL32, 4) ELF_RELOC(R_AMDGPU_REL32, 4)
ELF_RELOC(R_AMDGPU_REL64, 5) ELF_RELOC(R_AMDGPU_REL64, 5)
ELF_RELOC(R_AMDGPU_ABS32, 6) ELF_RELOC(R_AMDGPU_ABS32, 6)
ELF_RELOC(R_AMDGPU_GOTPCREL, 7) ELF_RELOC(R_AMDGPU_GOTPCREL, 7)
ELF_RELOC(R_AMDGPU_GOTPCREL32_LO, 8)
ELF_RELOC(R_AMDGPU_GOTPCREL32_HI, 9)
ELF_RELOC(R_AMDGPU_REL32_LO, 10)
ELF_RELOC(R_AMDGPU_REL32_HI, 11)

test/Object/AMDGPU/elf64-relocs.yaml

# RUN: yaml2obj %s > %t # RUN: yaml2obj %s > %t
# RUN: llvm-readobj -r %t | FileCheck %s # RUN: llvm-readobj -r %t | FileCheck %s
# CHECK: Relocations [ # CHECK: Relocations [
# CHECK: Section (2) .rela.text { # CHECK: Section (2) .rela.text {
# CHECK: 0x0 R_AMDGPU_NONE main 0x0 # CHECK: 0x0 R_AMDGPU_NONE - 0x0
# CHECK: 0x8 R_AMDGPU_ABS32_LO - 0x0 # CHECK: 0x2 R_AMDGPU_ABS32_LO - 0x0
# CHECK: 0x10 R_AMDGPU_ABS32_HI - 0x0 # CHECK: 0x4 R_AMDGPU_ABS32_HI - 0x0
# CHECK: 0x18 R_AMDGPU_ABS64 - 0x0 # CHECK: 0x6 R_AMDGPU_ABS64 - 0x0
# CHECK: 0x20 R_AMDGPU_REL32 - 0x0 # CHECK: 0x8 R_AMDGPU_REL32 - 0x0
# CHECK: 0x28 R_AMDGPU_REL64 - 0x0 # CHECK: 0x10 R_AMDGPU_REL64 - 0x0
# CHECK: 0x30 R_AMDGPU_ABS32 - 0x0 # CHECK: 0x12 R_AMDGPU_ABS32 - 0x0
# CHECK: 0x14 R_AMDGPU_GOTPCREL - 0x0
# CHECK: 0x16 R_AMDGPU_GOTPCREL32_LO - 0x0
# CHECK: 0x18 R_AMDGPU_GOTPCREL32_HI - 0x0
# CHECK: 0x20 R_AMDGPU_REL32_LO - 0x0
# CHECK: 0x22 R_AMDGPU_REL32_HI - 0x0
# CHECK: } # CHECK: }
# CHECK: ] # CHECK: ]
!ELF !ELF
FileHeader: FileHeader:
Class: ELFCLASS64 Class: ELFCLASS64
Data: ELFDATA2LSB Data: ELFDATA2LSB
Type: ET_REL Type: ET_REL
Machine: EM_AMDGPU Machine: EM_AMDGPU
Sections: Sections:
- Type: SHT_PROGBITS - Type: SHT_PROGBITS
Name: .text Name: .text
Flags: [ SHF_ALLOC, SHF_EXECINSTR ] Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
AddressAlign: 0x08 AddressAlign: 0x08
Content: 0000000000000000 Content: 0000000000000000
- Type: SHT_RELA - Type: SHT_RELA
Name: .rela.text Name: .rela.text
Link: .symtab Link: .symtab
Info: .text Info: .text
AddressAlign: 0x08 AddressAlign: 0x08
Relocations: Relocations:
- Offset: 0x0 - Offset: 0x0
Symbol: main Symbol: s0
Type: R_AMDGPU_NONE Type: R_AMDGPU_NONE
- Offset: 0x8 - Offset: 0x2
Symbol: a Symbol: s1
Type: R_AMDGPU_ABS32_LO Type: R_AMDGPU_ABS32_LO
- Offset: 0x10 - Offset: 0x4
Symbol: b Symbol: s2
Type: R_AMDGPU_ABS32_HI Type: R_AMDGPU_ABS32_HI
- Offset: 0x18 - Offset: 0x6
Symbol: c Symbol: s3
Type: R_AMDGPU_ABS64 Type: R_AMDGPU_ABS64
- Offset: 0x20 - Offset: 0x8
Symbol: d Symbol: s4
Type: R_AMDGPU_REL32 Type: R_AMDGPU_REL32
- Offset: 0x28 - Offset: 0x10
Symbol: e Symbol: s5
Type: R_AMDGPU_REL64 Type: R_AMDGPU_REL64
- Offset: 0x30 - Offset: 0x12
Symbol: f Symbol: s6
Type: R_AMDGPU_ABS32 Type: R_AMDGPU_ABS32
- Offset: 0x14
Symbol: s7
Type: R_AMDGPU_GOTPCREL
- Offset: 0x16
Symbol: s8
Type: R_AMDGPU_GOTPCREL32_LO
- Offset: 0x18
Symbol: s9
Type: R_AMDGPU_GOTPCREL32_HI
- Offset: 0x20
Symbol: s10
Type: R_AMDGPU_REL32_LO
- Offset: 0x22
Symbol: s11
Type: R_AMDGPU_REL32_HI
Symbols: Symbols:
Local: Local:
- Name: .text - Name: .text
Type: STT_SECTION Type: STT_SECTION
Section: .text Section: .text
Global: Global:
- Name: main - Name: main
Type: STT_FUNC Type: STT_FUNC
Section: .text Section: .text
Size: 0x08 Size: 0x08