[PPCMIPeephole] Fix splat elimination

[timshen]

Summary

In PPCMIPeephole, when we see two splat instructions, we can't simply do the following transformation:

B = Splat A
C = Splat B

>

C = Splat A

because B may still be used between these two instructions. Instead, we should make the second Splat a PPC::COPY and let later passes decide whether to remove it or not:

B = Splat A
C = Splat B

>

B = Splat A
C = COPY B

[echristo]

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

207

Should probably build rather than change in-place?

[timshen]

Updated to build a new instruction instead of mutating the original one.

[echristo]

LGTM.

Thanks!

-eric

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

for (MachineInstr &MI : MBB) {
         }
         break;
       }
       case PPC::VSPLTB:
       case PPC::VSPLTH:
       case PPC::XXSPLTW: {
         unsigned MyOpcode = MI.getOpcode();
         unsigned OpNo = MyOpcode == PPC::XXSPLTW ? 1 : 2;
+        unsigned UimNo = 3 - OpNo;
         unsigned TrueReg = lookThruCopyLike(MI.getOperand(OpNo).getReg());
         MachineInstr *DefMI = MRI->getVRegDef(TrueReg);
         if (!DefMI)
           break;
         unsigned DefOpcode = DefMI->getOpcode();
         bool SameOpcode = (MyOpcode == DefOpcode) ||
           (MyOpcode == PPC::VSPLTB && DefOpcode == PPC::VSPLTBs) ||
           (MyOpcode == PPC::VSPLTH && DefOpcode == PPC::VSPLTHs) ||
           (MyOpcode == PPC::XXSPLTW && DefOpcode == PPC::XXSPLTWs);
         // Splat fed by another splat - switch the output of the first
         // and remove the second.
         if (SameOpcode) {
-          DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
-          ToErase = &MI;
-          Simplified = true;
-          DEBUG(dbgs() << "Removing redundant splat: ");
+          DEBUG(dbgs() << "Changing redundant splat to a copy: ");
           DEBUG(MI.dump());
+          MI.setDesc(TII->get(PPC::COPY));
+          MI.RemoveOperand(UimNo);
+          Simplified = true;
         }
         // Splat fed by a shift. Usually when we align value to splat into
         // vector element zero.
         if (DefOpcode == PPC::XXSLDWI) {
           unsigned ShiftRes = DefMI->getOperand(0).getReg();
           unsigned ShiftOp1 = DefMI->getOperand(1).getReg();
           unsigned ShiftOp2 = DefMI->getOperand(2).getReg();
           unsigned ShiftImm = DefMI->getOperand(3).getImm();

llvm/test/CodeGen/PowerPC/pr30663.ll

+; RUN: llc -O1 < %s | FileCheck %s
+target triple = "powerpc64le-linux-gnu"
+
+; The second xxspltw should be eliminated.
+; CHECK: xxspltw
+; CHECK-NOT: xxspltw
+define void @Test() {
+bb4:
+  %tmp = load <4 x i8>, <4 x i8>* undef
+  %tmp8 = bitcast <4 x i8> %tmp to float
+  %tmp18 = fmul float %tmp8, undef
+  %tmp19 = fsub float 0.000000e+00, %tmp18
+  store float %tmp19, float* undef
+  %tmp22 = shufflevector <4 x i8> %tmp, <4 x i8> undef, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
+  %tmp23 = bitcast <16 x i8> %tmp22 to <4 x float>
+  %tmp25 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> undef, <4 x float> %tmp23, <4 x float> undef)
+  %tmp26 = fsub <4 x float> zeroinitializer, %tmp25
+  %tmp27 = bitcast <4 x float> %tmp26 to <4 x i32>
+  tail call void @llvm.ppc.altivec.stvx(<4 x i32> %tmp27, i8* undef)
+  ret void
+}
+
+declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*)
+declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)