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Differential D25312

AMDGPU: Fix use-after-frees
ClosedPublic

Authored by nhaehnle on Oct 6 2016, 4:51 AM.

Details

Reviewers
• tstellarAMD
arsenm
Commits
rGbd15c3267fa2: AMDGPU: Fix use-after-frees
rL284215: AMDGPU: Fix use-after-frees

Diff Detail

Event Timeline

nhaehnle updated this revision to Diff 73764.Oct 6 2016, 4:51 AM
nhaehnle retitled this revision from to AMDGPU: Fix use-after-frees.
nhaehnle updated this object.
nhaehnle added reviewers: arsenm, • tstellarAMD.
nhaehnle added a subscriber: llvm-commits.
Herald edited edge metadata. · View Herald TranscriptOct 6 2016, 4:51 AM
Herald added subscribers: tony-tye, yaxunl, wdng, kzhuravl. · View Herald Transcript
• tstellarAMD accepted this revision.Oct 7 2016, 6:59 AM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Oct 7 2016, 6:59 AM
Closed by commit rL284215: AMDGPU: Fix use-after-frees (authored by nha). · Explain WhyOct 14 2016, 2:12 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
18 lines
2 lines

Diff 73764

lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 1,299 Lines • ▼ Show 20 Linesstatic MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
const SISubtarget &ST) { const SISubtarget &ST) {
const SIInstrInfo *TII = ST.getInstrInfo(); const SIInstrInfo *TII = ST.getInstrInfo();
const SIRegisterInfo &TRI = TII->getRegisterInfo(); const SIRegisterInfo &TRI = TII->getRegisterInfo();
MachineFunction *MF = MBB.getParent(); MachineFunction *MF = MBB.getParent();
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
unsigned Dst = MI.getOperand(0).getReg(); unsigned Dst = MI.getOperand(0).getReg();
const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); unsigned SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm(); int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
unsigned SubReg; unsigned SubReg;
std::tie(SubReg, Offset) std::tie(SubReg, Offset)
= computeIndirectRegAndOffset(TRI, VecRC, SrcVec->getReg(), Offset); = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset)) { if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset)) {
MachineBasicBlock::iterator I(&MI); MachineBasicBlock::iterator I(&MI);
const DebugLoc &DL = MI.getDebugLoc(); const DebugLoc &DL = MI.getDebugLoc();
BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst) BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
.addReg(SrcVec->getReg(), RegState::Undef, SubReg) .addReg(SrcReg, RegState::Undef, SubReg)
.addReg(SrcVec->getReg(), RegState::Implicit); .addReg(SrcReg, RegState::Implicit);
MI.eraseFromParent(); MI.eraseFromParent();
return &MBB; return &MBB;
} }
const DebugLoc &DL = MI.getDebugLoc(); const DebugLoc DL = MI.getDebugLoc();
MachineBasicBlock::iterator I(&MI); MachineBasicBlock::iterator I(&MI);
unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); unsigned InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg); BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset); auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset);
BuildMI(*InsPt->getParent(), InsPt, DL, BuildMI(*InsPt->getParent(), InsPt, DL,
TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst) TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
.addReg(SrcVec->getReg(), RegState::Undef, SubReg) .addReg(SrcReg, RegState::Undef, SubReg)
.addReg(SrcVec->getReg(), RegState::Implicit); .addReg(SrcReg, RegState::Implicit);
return InsPt->getParent(); return InsPt->getParent();
} }
static MachineBasicBlock *emitIndirectDst(MachineInstr &MI, static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
const SISubtarget &ST) { const SISubtarget &ST) {
const SIInstrInfo *TII = ST.getInstrInfo(); const SIInstrInfo *TII = ST.getInstrInfo();
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset)) {
MovRel->tieOperands(ImpDefIdx, ImpUseIdx); MovRel->tieOperands(ImpDefIdx, ImpUseIdx);
MI.eraseFromParent(); MI.eraseFromParent();
return &MBB; return &MBB;
} }
if (Val->isReg()) if (Val->isReg())
MRI.clearKillFlags(Val->getReg()); MRI.clearKillFlags(Val->getReg());
const DebugLoc &DL = MI.getDebugLoc(); const DebugLoc DL = MI.getDebugLoc();
unsigned PhiReg = MRI.createVirtualRegister(VecRC); unsigned PhiReg = MRI.createVirtualRegister(VecRC);
auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset); auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg, Offset);
// vdst is not actually read and just provides the base register index. // vdst is not actually read and just provides the base register index.
MachineInstr *MovRel = MachineInstr *MovRel =
BuildMI(*InsPt->getParent(), InsPt, DL, MovRelDesc) BuildMI(*InsPt->getParent(), InsPt, DL, MovRelDesc)
.addReg(PhiReg, RegState::Undef, SubReg) // vdst .addReg(PhiReg, RegState::Undef, SubReg) // vdst
▲ Show 20 Lines • Show All 2,474 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SIRegisterInfo.cpp

Show First 20 Lines • Show All 605 Lines • ▼ Show 20 Lines switch (MI->getOpcode()) {
case AMDGPU::SI_SPILL_V64_SAVE: case AMDGPU::SI_SPILL_V64_SAVE:
case AMDGPU::SI_SPILL_V32_SAVE: case AMDGPU::SI_SPILL_V32_SAVE:
buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET, buildScratchLoadStore(MI, AMDGPU::BUFFER_STORE_DWORD_OFFSET,
TII->getNamedOperand(*MI, AMDGPU::OpName::vdata), TII->getNamedOperand(*MI, AMDGPU::OpName::vdata),
TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(), TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(),
TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(), TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg(),
FrameInfo.getObjectOffset(Index) + FrameInfo.getObjectOffset(Index) +
TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS); TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), RS);
MI->eraseFromParent();
MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode())); MFI->addToSpilledVGPRs(getNumSubRegsForSpillOp(MI->getOpcode()));
MI->eraseFromParent();
break; break;
case AMDGPU::SI_SPILL_V32_RESTORE: case AMDGPU::SI_SPILL_V32_RESTORE:
case AMDGPU::SI_SPILL_V64_RESTORE: case AMDGPU::SI_SPILL_V64_RESTORE:
case AMDGPU::SI_SPILL_V96_RESTORE: case AMDGPU::SI_SPILL_V96_RESTORE:
case AMDGPU::SI_SPILL_V128_RESTORE: case AMDGPU::SI_SPILL_V128_RESTORE:
case AMDGPU::SI_SPILL_V256_RESTORE: case AMDGPU::SI_SPILL_V256_RESTORE:
case AMDGPU::SI_SPILL_V512_RESTORE: { case AMDGPU::SI_SPILL_V512_RESTORE: {
buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET, buildScratchLoadStore(MI, AMDGPU::BUFFER_LOAD_DWORD_OFFSET,
▲ Show 20 Lines • Show All 447 Lines • Show Last 20 Lines