AArch64: Complete macroop fusion lists.

[MatzeB]

Summary

AArch64InstrInfo::shouldScheduleAdjacent() determines whether two instruction can benefit from macroop fusion.
Until recently macrofusion was only enabled for Apple CPUs and this list was designed for that. As it turned out it was not complete and needed more entries, which this patch fixes.

However by now the macrofusion code appears to be used by Vulcan CPU as well. Pankaj: Can you comment whether those changes are good for vulcan as well or whether we have to find a way to split this into vulcan and apple specific code?

This is an early patch to get review comments, testcase adjustments still pending.

[pgode]

Thanks for asking.
The first part of changes i.e. 'Fuse CMN, CMP, TST followed by Bcc', is applicable for Vulcan as well.
But, the second part i.e. 'Fuse ALU operations followed by CBZ/CBNZ' is not applicable for Vulcan, i.e. we don't fuse these. Is it possible to make this only Apple specific ?

[MatzeB]

In D25142#558567, @pgode wrote:

Thanks for asking.
The first part of changes i.e. 'Fuse CMN, CMP, TST followed by Bcc', is applicable for Vulcan as well.
But, the second part i.e. 'Fuse ALU operations followed by CBZ/CBNZ' is not applicable for Vulcan, i.e. we don't fuse these. Is it possible to make this only Apple specific ?

That part was even there before the patch. Anyway I'll update the patch by splitting the target feature into two.

[MatzeB]

Split macrofusion target feature into two so we can model the apple/vulcan differences.

[pgode]

Thanks for splitting the code. LGTM.
Thanks.

lib/Target/AArch64/AArch64InstrInfo.cpp

bool AArch64InstrInfo::shouldClusterMemOps(MachineInstr &FirstLdSt,
   // The caller should already have ordered First/SecondLdSt by offset.
   assert(Offset1 <= Offset2 && "Caller should have ordered offsets.");
   return Offset1 + 1 == Offset2;
 }
 
 bool AArch64InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
                                               MachineInstr &Second) const {
   if (Subtarget.hasMacroOpFusion()) {
+    // Macrofusion rules for Apple Cyclone and newer.
+
     // Fuse CMN, CMP, TST followed by Bcc.
     unsigned SecondOpcode = Second.getOpcode();
     if (SecondOpcode == AArch64::Bcc) {
       switch (First.getOpcode()) {
       default:
         return false;
-      case AArch64::SUBSWri:
       case AArch64::ADDSWri:
-      case AArch64::ANDSWri:
-      case AArch64::SUBSXri:
+      case AArch64::ADDSWrr:
       case AArch64::ADDSXri:
+      case AArch64::ADDSXrr:
+      case AArch64::ANDSWri:
+      case AArch64::ANDSWrr:
       case AArch64::ANDSXri:
+      case AArch64::ANDSXrr:
+      case AArch64::SUBSWri:
+      case AArch64::SUBSWrr:
+      case AArch64::SUBSXri:
+      case AArch64::SUBSXrr:
+      case AArch64::BICSWrr:
+      case AArch64::BICSXrr:
         return true;
+      case AArch64::ADDSWrs:
+      case AArch64::ADDSXrs:
+      case AArch64::ANDSWrs:
+      case AArch64::ANDSXrs:
+      case AArch64::SUBSWrs:
+      case AArch64::SUBSXrs:
+      case AArch64::BICSWrs:
+      case AArch64::BICSXrs:
+        // Shift value can be 0 making these behave like the "rr" variant...
+        return !hasShiftedReg(Second);
       }
     }
     // Fuse ALU operations followed by CBZ/CBNZ.
     if (SecondOpcode == AArch64::CBNZW || SecondOpcode == AArch64::CBNZX ||
         SecondOpcode == AArch64::CBZW || SecondOpcode == AArch64::CBZX) {
       switch (First.getOpcode()) {
       default:
         return false;
       case AArch64::ADDWri:
+      case AArch64::ADDWrr:
       case AArch64::ADDXri:
+      case AArch64::ADDXrr:
       case AArch64::ANDWri:
+      case AArch64::ANDWrr:
       case AArch64::ANDXri:
+      case AArch64::ANDXrr:
       case AArch64::EORWri:
+      case AArch64::EORWrr:
       case AArch64::EORXri:
+      case AArch64::EORXrr:
       case AArch64::ORRWri:
+      case AArch64::ORRWrr:
       case AArch64::ORRXri:
+      case AArch64::ORRXrr:
       case AArch64::SUBWri:
+      case AArch64::SUBWrr:
       case AArch64::SUBXri:
+      case AArch64::SUBXrr:
         return true;
+      case AArch64::ADDWrs:
+      case AArch64::ADDXrs:
+      case AArch64::ANDWrs:
+      case AArch64::ANDXrs:
+      case AArch64::SUBWrs:
+      case AArch64::SUBXrs:
+      case AArch64::BICWrs:
+      case AArch64::BICXrs:
+        // Shift value can be 0 making these behave like the "rr" variant...
+        return !hasShiftedReg(Second);
       }
     }
   }
   return false;
 }
 
 MachineInstr *AArch64InstrInfo::emitFrameIndexDebugValue(
     MachineFunction &MF, int FrameIx, uint64_t Offset, const MDNode *Var,