[x86][inline-asm][llvm] accept 'v' constraint

[coby]

Summary

1. 'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64).
2. for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent)

This patch applies the needed changes to clang
clang patch: https://reviews.llvm.org/D25004

[delena]

lib/Target/X86/X86ISelLowering.cpp

32380

you can use FR32X if you have VLX. Otherwise take FR32. The same about other cases.

32385

line alignment

test/CodeGen/X86/inline-asm-avx512-v-constraint.ll

1 ↗

(On Diff #72770)

you also should check knl.
Community asks to avoid -mcpu flag and use -march instead. (I don't know why)

[coby]

Addressing comments:

1. Added more robust tests
2. Refined EVEX-accessible registers selection

[delena]

In my opinion, you did not write enough tests. You should cover AVX512F more with zmm, ymm, xmm, multiple instructions.
You also should check error messages, when user puts wrong registers.

lib/Target/X86/X86ISelLowering.cpp

32036

does 'v' work without avx512?

32386

FR64 and FR64X will not work for i64 and i32 . Please add a test that checks this.

32406

you can remove Subtarget.hasAVX512(). VLX includes AV512

test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll

3

-mattr -avx512vl is redundant, you can remove the second run.

[coby]

Addressing Elena's comments

[coby]

Uploading correct diff

[coby]

Commitd to revision 283717

lib/Target/X86/X86ISelLowering.cpp

if (Constraint.size() == 1) {
     case 'R':
     case 'q':
     case 'Q':
     case 'f':
     case 't':
     case 'u':
     case 'y':
     case 'x':
+    case 'v':
     case 'Y':
     case 'l':
       return C_RegisterClass;
     case 'a':
     case 'b':
     case 'c':
     case 'd':
     case 'S':
TargetLowering::ConstraintWeight
   case 'u':
     if (type->isFloatingPointTy())
       weight = CW_SpecificReg;
     break;
   case 'y':
     if (type->isX86_MMXTy() && Subtarget.hasMMX())
       weight = CW_SpecificReg;
     break;
+  case 'v':
+    if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
+      weight = CW_Register;
+    LLVM_FALLTHROUGH;
   case 'x':
   case 'Y':
     if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
         ((type->getPrimitiveSizeInBits() == 256) && Subtarget.hasFp256()))
       weight = CW_Register;
     break;
   case 'I':
     if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) {
       if (C->getZExtValue() <= 31)
         weight = CW_Constant;
     }
case 'f':  // FP Stack registers.
         return std::make_pair(0U, &X86::RFP64RegClass);
       return std::make_pair(0U, &X86::RFP80RegClass);
     case 'y':   // MMX_REGS if MMX allowed.
       if (!Subtarget.hasMMX()) break;
       return std::make_pair(0U, &X86::VR64RegClass);
     case 'Y':   // SSE_REGS if SSE2 allowed
       if (!Subtarget.hasSSE2()) break;
       LLVM_FALLTHROUGH;
+    case 'v':
     case 'x':   // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
       if (!Subtarget.hasSSE1()) break;
+      bool VConstraint = (Constraint[0] == 'v');
 
       switch (VT.SimpleTy) {
       default: break;
       // Scalar SSE types.
       case MVT::f32:
       case MVT::i32:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::FR32XRegClass);
         return std::make_pair(0U, &X86::FR32RegClass);
       case MVT::f64:
       case MVT::i64:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::FR64XRegClass);
         return std::make_pair(0U, &X86::FR64RegClass);
       // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
       // Vector types.
       case MVT::v16i8:
       case MVT::v8i16:
       case MVT::v4i32:
       case MVT::v2i64:
       case MVT::v4f32:
       case MVT::v2f64:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::VR128XRegClass);
         return std::make_pair(0U, &X86::VR128RegClass);
       // AVX types.
       case MVT::v32i8:
       case MVT::v16i16:
       case MVT::v8i32:
       case MVT::v4i64:
       case MVT::v8f32:
       case MVT::v4f64:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::VR256XRegClass);
         return std::make_pair(0U, &X86::VR256RegClass);
       case MVT::v8f64:
       case MVT::v16f32:
       case MVT::v16i32:
       case MVT::v8i64:
         return std::make_pair(0U, &X86::VR512RegClass);
       }
       break;

test/CodeGen/X86/inline-asm-avx-v-constraint.ll

+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx | FileCheck %s
+
+; CHECK: vmovhlps        %xmm1, %xmm0, %xmm0
+define <4 x float> @testXMM(<4 x float> %_xmm0, i64 %_l) local_unnamed_addr {
+entry:
+  %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
+  ret <4 x float> %0
+}
+
+; CHECK: vmovsldup       %ymm0, %ymm0
+define <8 x float> @testYMM(<8 x float> %_ymm0) local_unnamed_addr {
+entry:
+  %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0)
+  ret <8 x float> %0
+}
+

test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll

+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx512vl | FileCheck %s
+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx512f -mattr -avx512vl | FileCheck %s
+
+; CHECK: vpternlogd      $0, %zmm1, %zmm0
+define <16 x float> @testZMM(<16 x float> %_zmm0, <16 x float> %_zmm1) local_unnamed_addr {
+entry:
+  %0 = tail call <16 x float> asm "vpternlogd $$0, $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm0)
+  ret <16 x float> %0
+}
+

test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll

+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx512VL | FileCheck %s
+
+; CHECK: vmovhlps        %xmm17, %xmm16, %xmm16
+define <4 x float> @testXMM(<4 x float> %_xmm0, i64 %_l) local_unnamed_addr {
+entry:
+  %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
+  ret <4 x float> %0
+}
+
+; CHECK: vmovsldup       %ymm16, %ymm16
+define <8 x float> @testYMM(<8 x float> %_ymm0) local_unnamed_addr {
+entry:
+  %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0)
+  ret <8 x float> %0
+}
+
+