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Differential D24765

[AMDGPU][mc] Add support for ds_add_[rtn_]f32.
ClosedPublic

Authored by artem.tamazov on Sep 20 2016, 7:42 AM.

Details

Reviewers
• tstellarAMD
vpykhtin
SamWot
Commits
rG2e217b87cbd8: [AMDGPU][mc] Add support for ds_add_[rtn_]f32.
rL282086: [AMDGPU][mc] Add support for ds_add_[rtn_]f32.
Summary

Lit tests added.
Resolves https://github.com/RadeonOpenCompute/hcc/issues/122.

Diff Detail

Repository
rL LLVM

Event Timeline

artem.tamazov updated this revision to Diff 71931.Sep 20 2016, 7:42 AM
artem.tamazov retitled this revision from to [AMDGPU][mc] Add support for ds_add_[rtn_]f32..
artem.tamazov updated this object.
artem.tamazov added a reviewer: vpykhtin.
artem.tamazov set the repository for this revision to rL LLVM.
artem.tamazov added a subscriber: Restricted Project.
Herald added a reviewer: • tstellarAMD. · View Herald TranscriptSep 20 2016, 7:42 AM
Herald added subscribers: tony-tye, yaxunl, nhaehnle and 3 others. · View Herald Transcript
vpykhtin accepted this revision.Sep 20 2016, 11:48 AM
vpykhtin edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Sep 20 2016, 11:48 AM
SamWot accepted this revision.Sep 21 2016, 3:55 AM
SamWot added a reviewer: SamWot.
SamWot added a subscriber: SamWot.

LGTM

Closed by commit rL282086: [AMDGPU][mc] Add support for ds_add_[rtn_]f32. (authored by artem.tamazov). · Explain WhySep 21 2016, 9:44 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
5 lines
test/
MC/
AMDGPU/
17 lines

Diff 71931

lib/Target/AMDGPU/DSInstructions.td

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def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">; def DS_DEC_U32 : DS_1A1D_NORET<"ds_dec_u32">;
def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">; def DS_MIN_I32 : DS_1A1D_NORET<"ds_min_i32">;
def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">; def DS_MAX_I32 : DS_1A1D_NORET<"ds_max_i32">;
def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">; def DS_MIN_U32 : DS_1A1D_NORET<"ds_min_u32">;
def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">; def DS_MAX_U32 : DS_1A1D_NORET<"ds_max_u32">;
def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">; def DS_AND_B32 : DS_1A1D_NORET<"ds_and_b32">;
def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">; def DS_OR_B32 : DS_1A1D_NORET<"ds_or_b32">;
def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">; def DS_XOR_B32 : DS_1A1D_NORET<"ds_xor_b32">;
def DS_ADD_F32 : DS_1A1D_NORET<"ds_add_f32">;
let mayLoad = 0 in { let mayLoad = 0 in {
def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">; def DS_WRITE_B8 : DS_1A1D_NORET<"ds_write_b8">;
def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">; def DS_WRITE_B16 : DS_1A1D_NORET<"ds_write_b16">;
def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">; def DS_WRITE_B32 : DS_1A1D_NORET<"ds_write_b32">;
def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">; def DS_WRITE2_B32 : DS_1A2D_Off8_NORET<"ds_write2_b32">;
def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">; def DS_WRITE2ST64_B32 : DS_1A2D_Off8_NORET<"ds_write2st64_b32">;
} }
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} }
def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>; def DS_CMPST_B64 : DS_1A2D_NORET<"ds_cmpst_b64", VReg_64>;
def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>; def DS_CMPST_F64 : DS_1A2D_NORET<"ds_cmpst_f64", VReg_64>;
def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>; def DS_MIN_F64 : DS_1A1D_NORET<"ds_min_f64", VReg_64>;
def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>; def DS_MAX_F64 : DS_1A1D_NORET<"ds_max_f64", VReg_64>;
def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">, def DS_ADD_RTN_U32 : DS_1A1D_RET<"ds_add_rtn_u32">,
AtomicNoRet<"ds_add_u32", 1>; AtomicNoRet<"ds_add_u32", 1>;
def DS_ADD_RTN_F32 : DS_1A1D_RET<"ds_add_rtn_f32">,
AtomicNoRet<"ds_add_f32", 1>;
def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">, def DS_SUB_RTN_U32 : DS_1A1D_RET<"ds_sub_rtn_u32">,
AtomicNoRet<"ds_sub_u32", 1>; AtomicNoRet<"ds_sub_u32", 1>;
def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">, def DS_RSUB_RTN_U32 : DS_1A1D_RET<"ds_rsub_rtn_u32">,
AtomicNoRet<"ds_rsub_u32", 1>; AtomicNoRet<"ds_rsub_u32", 1>;
def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">, def DS_INC_RTN_U32 : DS_1A1D_RET<"ds_inc_rtn_u32">,
AtomicNoRet<"ds_inc_u32", 1>; AtomicNoRet<"ds_inc_u32", 1>;
def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">, def DS_DEC_RTN_U32 : DS_1A1D_RET<"ds_dec_rtn_u32">,
AtomicNoRet<"ds_dec_u32", 1>; AtomicNoRet<"ds_dec_u32", 1>;
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def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>; def DS_MSKOR_B32_vi : DS_Real_vi<0xc, DS_MSKOR_B32>;
def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>; def DS_WRITE_B32_vi : DS_Real_vi<0xd, DS_WRITE_B32>;
def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>; def DS_WRITE2_B32_vi : DS_Real_vi<0xe, DS_WRITE2_B32>;
def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>; def DS_WRITE2ST64_B32_vi : DS_Real_vi<0xf, DS_WRITE2ST64_B32>;
def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>; def DS_CMPST_B32_vi : DS_Real_vi<0x10, DS_CMPST_B32>;
def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>; def DS_CMPST_F32_vi : DS_Real_vi<0x11, DS_CMPST_F32>;
def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>; def DS_MIN_F32_vi : DS_Real_vi<0x12, DS_MIN_F32>;
def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>; def DS_MAX_F32_vi : DS_Real_vi<0x13, DS_MAX_F32>;
def DS_ADD_F32_vi : DS_Real_vi<0x15, DS_ADD_F32>;
def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>; def DS_GWS_INIT_vi : DS_Real_vi<0x19, DS_GWS_INIT>;
def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>; def DS_GWS_SEMA_V_vi : DS_Real_vi<0x1a, DS_GWS_SEMA_V>;
def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>; def DS_GWS_SEMA_BR_vi : DS_Real_vi<0x1b, DS_GWS_SEMA_BR>;
def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>; def DS_GWS_SEMA_P_vi : DS_Real_vi<0x1c, DS_GWS_SEMA_P>;
def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>; def DS_GWS_BARRIER_vi : DS_Real_vi<0x1d, DS_GWS_BARRIER>;
def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>; def DS_WRITE_B8_vi : DS_Real_vi<0x1e, DS_WRITE_B8>;
def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>; def DS_WRITE_B16_vi : DS_Real_vi<0x1f, DS_WRITE_B16>;
def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>; def DS_ADD_RTN_U32_vi : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
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def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>; def DS_WRXCHG_RTN_B32_vi : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>; def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>; def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>; def DS_CMPST_RTN_B32_vi : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>; def DS_CMPST_RTN_F32_vi : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>; def DS_MIN_RTN_F32_vi : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>; def DS_MAX_RTN_F32_vi : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>; def DS_WRAP_RTN_F32_vi : DS_Real_vi<0x34, DS_WRAP_RTN_F32>;
def DS_ADD_RTN_F32_vi : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>; def DS_READ_B32_vi : DS_Real_vi<0x36, DS_READ_B32>;
def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>; def DS_READ2_B32_vi : DS_Real_vi<0x37, DS_READ2_B32>;
def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>; def DS_READ2ST64_B32_vi : DS_Real_vi<0x38, DS_READ2ST64_B32>;
def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>; def DS_READ_I8_vi : DS_Real_vi<0x39, DS_READ_I8>;
def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>; def DS_READ_U8_vi : DS_Real_vi<0x3a, DS_READ_U8>;
def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>; def DS_READ_I16_vi : DS_Real_vi<0x3b, DS_READ_I16>;
def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>; def DS_READ_U16_vi : DS_Real_vi<0x3c, DS_READ_U16>;
def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>; def DS_SWIZZLE_B32_vi : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
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test/MC/AMDGPU/ds.s

// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SICI // RUN: not llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s --check-prefix=SI --check-prefix=SICI
// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s --check-prefix=SICI // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s | FileCheck %s --check-prefix=SI --check-prefix=SICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s | FileCheck %s --check-prefix=CI --check-prefix=SICI
// RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI // RUN: llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck %s --check-prefix=VI
// RUN: not llvm-mc -arch=amdgcn -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOSI --check-prefix=NOSICI
// RUN: not llvm-mc -arch=amdgcn -mcpu=bonaire -show-encoding %s 2>&1 | FileCheck %s --check-prefix=NOCI --check-prefix=NOSICI
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Checks for 16-bit Offsets // Checks for 16-bit Offsets
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
ds_add_u32 v2, v4 offset:16 ds_add_u32 v2, v4 offset:16
// SICI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] // VI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instructions // Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
ds_add_u32 v2, v4 ds_add_u32 v2, v4
// SICI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00] // VI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
ds_add_f32 v2, v4
// NOSICI: error: instruction not supported on this GPU
// VI: ds_add_f32 v2, v4 ; encoding: [0x00,0x00,0x2a,0xd8,0x02,0x04,0x00,0x00]
ds_sub_u32 v2, v4 ds_sub_u32 v2, v4
// SICI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00] // VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00]
ds_rsub_u32 v2, v4 ds_rsub_u32 v2, v4
// SICI: ds_rsub_u32 v2, v4 ; encoding: [0x00,0x00,0x08,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_rsub_u32 v2, v4 ; encoding: [0x00,0x00,0x08,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_rsub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00] // VI: ds_rsub_u32 v2, v4 ; encoding: [0x00,0x00,0x04,0xd8,0x02,0x04,0x00,0x00]
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ds_write_b16 v2, v4 ds_write_b16 v2, v4
// SICI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x7c,0xd8,0x02,0x04,0x00,0x00] // SICI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x7c,0xd8,0x02,0x04,0x00,0x00]
// VI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x3e,0xd8,0x02,0x04,0x00,0x00] // VI: ds_write_b16 v2, v4 ; encoding: [0x00,0x00,0x3e,0xd8,0x02,0x04,0x00,0x00]
ds_add_rtn_u32 v8, v2, v4 ds_add_rtn_u32 v8, v2, v4
// SICI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x08] // SICI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x80,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08] // VI: ds_add_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x40,0xd8,0x02,0x04,0x00,0x08]
ds_add_rtn_f32 v8, v2, v4
// NOSICI: error: instruction not supported on this GPU
// VI: ds_add_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x6a,0xd8,0x02,0x04,0x00,0x08]
ds_sub_rtn_u32 v8, v2, v4 ds_sub_rtn_u32 v8, v2, v4
// SICI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x84,0xd8,0x02,0x04,0x00,0x08] // SICI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x84,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x42,0xd8,0x02,0x04,0x00,0x08] // VI: ds_sub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x42,0xd8,0x02,0x04,0x00,0x08]
ds_rsub_rtn_u32 v8, v2, v4 ds_rsub_rtn_u32 v8, v2, v4
// SICI: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x88,0xd8,0x02,0x04,0x00,0x08] // SICI: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x88,0xd8,0x02,0x04,0x00,0x08]
// VI: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x00,0x08] // VI: ds_rsub_rtn_u32 v8, v2, v4 ; encoding: [0x00,0x00,0x44,0xd8,0x02,0x04,0x00,0x08]
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