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[AArch64] Improve add/sub/cmp isel of uxtw forms.
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Authored by gberry on Sep 19 2016, 2:49 PM.

Details

Summary

Don't match the UXTW extended reg forms of ADD/ADDS/SUB/SUBS if the
32-bit to 64-bit zero-extend can be done for free by taking advantage
of the 32-bit defining instruction zeroing the upper 32-bits of the X
register destination. This enables better instruction selection in a
few cases, such as:

  
sub x0, xzr, x8
instead of:
mov x8, xzr
sub x0, x8, w9, uxtw
  
madd x0, x1, x1, x8
instead of:
mul x9, x1, x1
add x0, x9, w8, uxtw
  
cmp x2, x8
instead of:
sub x8, x2, w8, uxtw
cmp x8, #0
  
add x0, x8, x1, lsl #3
instead of:
lsl x9, x1, #3
add x0, x9, w8, uxtw

Diff Detail

Event Timeline

gberry updated this revision to Diff 71883.Sep 19 2016, 2:49 PM
gberry retitled this revision from to [AArch64] Improve isel of negate of zext..
gberry updated this object.
gberry added reviewers: t.p.northover, jmolloy.
gberry added subscribers: llvm-commits, mcrosier.

LGTM, but I'd be interested to hear feedback from @jmolloy or @t.p.northover.

lib/Target/AArch64/AArch64InstrInfo.td
313

Not your fault, but maybe fix the wording of the first sentence..

"..leaves the high half of the register zeroed."

Feel free to commit as a separate patch.

t.p.northover edited edge metadata.Sep 20 2016, 3:51 AM

Aren't other instructions affected too? Add at least ought to be symmetric, and quite possibly some logical operations.

Aren't other instructions affected too? Add at least ought to be symmetric, and quite possibly some logical operations.

I believe ADD/ADDS are the only other instructions with UXTW forms. I didn't think those would be interesting since they shouldn't ever have a known 0 as an operand, but I tried it anyway, and it does end up making a difference (by, for example, generating more madds). I'm still working on tinkering with the AddedComplexity and adding more patterns to avoid regressions, but this should end up having more of an impact than I initially thought.

gberry updated this revision to Diff 72092.Sep 21 2016, 12:24 PM
gberry edited edge metadata.

New much simpler version.

gberry retitled this revision from [AArch64] Improve isel of negate of zext. to [AArch64] Improve add/sub/cmp isel of uxtw forms..Sep 21 2016, 12:25 PM
gberry updated this object.
t.p.northover accepted this revision.Sep 26 2016, 3:21 AM
t.p.northover edited edge metadata.

This looks fine to me. Thanks!

This revision is now accepted and ready to land.Sep 26 2016, 3:21 AM
This revision was automatically updated to reflect the committed changes.