AArch64: Set shift bit of TLSLE HI12 add instruction

[lliu0]

Summary

AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model. This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.

[lliu0]

This is to fix https://llvm.org/bugs/show_bug.cgi?id=30436.

[rovka]

Could you please add a testcase for this? You can use llvm-objdump -r -d to make sure you got the right encoding and relocation.
The fix itself seems ok. Maybe we should consider doing the same thing for DTPREL? (I'm not sure gcc supports DTPREL atm, but we do, so we should be consistent).

[lliu0]

Set shift bit for R_AARCH64_TLSLD_ADD_DTPREL_HI12 as well.
Added test case.

[rovka]

LGTM, thanks.

[lliu0]

Fix AArch64 test breakage.

FAIL: LLVM::frameindices.ll
FAIL: LLVM::arm64-tls-modifiers-darwin.s
FAIL: LLVM::darwin-reloc-addsubimm.s

[rengolin]

Hi Lei,

Did you run "make check-all" with this patch? It seem to have broken on multiple buildbots, ARM, AArch64, PPC, etc.

cheers,
--renato

[lliu0]

Hi Renato,

I have run "make check-all" with my latest change (Diff 72029).

Scanning dependencies of target check-all
[100%] Running all regression tests
Testing Time: 215.37s

Expected Passes    : 17686
Expected Failures  : 124
Unsupported Tests  : 222

[100%] Built target check-all

I think it's good now.

[rovka]

lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

268

I think the intent would be clearer if you folded this check and the cast below into a dyn_cast (http://llvm.org/docs/ProgrammersManual.html#isa).

[rovka]

Nit: you can move the declaration of A64E in if's condition.
I think this is ok to commit now if it passes check-all.

[lliu0]

Make check-all passed with the change.

In D24702#550475, @rovka wrote:

Nit: you can move the declaration of A64E in if's condition.
I think this is ok to commit now if it passes check-all.

lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

 
   ++MCNumFixups;
 
+  // Set the shift bit of the add instruction for relocation types
+  // R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12.
+  if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) {
+    AArch64MCExpr::VariantKind RefKind = A64E->getKind();
+    if (RefKind == AArch64MCExpr::VK_TPREL_HI12 ||
+        RefKind == AArch64MCExpr::VK_DTPREL_HI12)
+      ShiftVal = 12;
+  }
   return ShiftVal == 0 ? 0 : (1 << ShiftVal);
 }
 

test/MC/AArch64/tls-add-shift.s

+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \
+// RUN:   llvm-objdump -r -d - | FileCheck %s
+
+  // TLS add TPREL
+  add x2, x1, #:tprel_hi12:var
+// CHECK: add x2, x1, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+
+  // TLS add DTPREL
+  add x4, x3, #:dtprel_hi12:var
+// CHECK: add x4, x3, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLD_ADD_DTPREL_HI12 var