AMDGPU/SI: Use new SimplifyDemandedBits helper for multi-use operations

[• tstellarAMD]

Summary

We are using this helper for our 24-bit arithmetic combines, so we are now able to eliminate multi-use operations that mask the high-bits of 24-bit inputs (e.g. and x, 0xffffff)

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2441–2449 ↗

(On Diff #71656)

This looks like an overly specific version of computeKnownBits. I was trying to figure out how to factor SimplifyDemandedBits to allow checking multiple uses but never got around to trying it

2444 ↗

(On Diff #71656)

unchecked dyn_cast

2459–2462 ↗

(On Diff #71656)

This can early exit if the first one failed

[arsenm]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2441–2449 ↗

(On Diff #71656)

For and this could also be >= 8

[• tstellarAMD]

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

2441–2449 ↗

(On Diff #71656)

I looked into it, but I thought the cost of doing that would be too high. One idea I had ws to add an extra parameter for when you wanted to consider multiple uses.

[• tstellarAMD]

Use new SimplifyDemandedBits helper to handle multiple uses.

[nhaehnle]

LGTM

llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

static bool isI24(SDValue Op, SelectionDAG &DAG) {
 
   // In order for this to be a signed 24-bit value, bit 23, must
   // be a sign bit.
   return VT.getSizeInBits() >= 24 && // Types less than 24-bit should be treated
                                      // as unsigned 24-bit values.
          (VT.getSizeInBits() - DAG.ComputeNumSignBits(Op)) < 24;
 }
 
-static bool simplifyI24(SDValue Op, TargetLowering::DAGCombinerInfo &DCI) {
+static bool simplifyI24(SDNode *Node24, unsigned OpIdx,
+                        TargetLowering::DAGCombinerInfo &DCI) {
 
   SelectionDAG &DAG = DCI.DAG;
-  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
+  SDValue Op = Node24->getOperand(OpIdx);
   EVT VT = Op.getValueType();
 
   APInt Demanded = APInt::getLowBitsSet(VT.getSizeInBits(), 24);
   APInt KnownZero, KnownOne;
   TargetLowering::TargetLoweringOpt TLO(DAG, true, true);
-  if (TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) {
-    DCI.CommitTargetLoweringOpt(TLO);
+  if (TLO.SimplifyDemandedBits(Node24, OpIdx, Demanded, DCI))
     return true;
-  }
 
   return false;
 }
 
 template <typename IntTy>
 static SDValue constantFoldBFE(SelectionDAG &DAG, IntTy Src0, uint32_t Offset,
                                uint32_t Width, const SDLoc &DL) {
   if (Width + Offset < 32) {
SDValue AMDGPUTargetLowering::performMulhuCombine(SDNode *N,
   DCI.AddToWorklist(Mulhi.getNode());
   return DAG.getZExtOrTrunc(Mulhi, DL, VT);
 }
 
 SDValue AMDGPUTargetLowering::performMulLoHi24Combine(
   SDNode *N, DAGCombinerInfo &DCI) const {
   SelectionDAG &DAG = DCI.DAG;
 
-  SDValue N0 = N->getOperand(0);
-  SDValue N1 = N->getOperand(1);
-
   // Simplify demanded bits before splitting into multiple users.
-  if (simplifyI24(N0, DCI) || simplifyI24(N1, DCI))
+  if (simplifyI24(N, 0, DCI) || simplifyI24(N, 1, DCI))
     return SDValue();
 
+  SDValue N0 = N->getOperand(0);
+  SDValue N1 = N->getOperand(1);
+
   bool Signed = (N->getOpcode() == AMDGPUISD::MUL_LOHI_I24);
 
   unsigned MulLoOpc = Signed ? AMDGPUISD::MUL_I24 : AMDGPUISD::MUL_U24;
   unsigned MulHiOpc = Signed ? AMDGPUISD::MULHI_I24 : AMDGPUISD::MULHI_U24;
 
   SDLoc SL(N);
 
   SDValue MulLo = DAG.getNode(MulLoOpc, SL, MVT::i32, N0, N1);
SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::MULHS:
     return performMulhsCombine(N, DCI);
   case ISD::MULHU:
     return performMulhuCombine(N, DCI);
   case AMDGPUISD::MUL_I24:
   case AMDGPUISD::MUL_U24:
   case AMDGPUISD::MULHI_I24:
   case AMDGPUISD::MULHI_U24: {
-    SDValue N0 = N->getOperand(0);
-    SDValue N1 = N->getOperand(1);
-    simplifyI24(N0, DCI);
-    simplifyI24(N1, DCI);
+    simplifyI24(N, 0, DCI);
+    simplifyI24(N, 1, DCI);
     return SDValue();
   }
   case AMDGPUISD::MUL_LOHI_I24:
   case AMDGPUISD::MUL_LOHI_U24:
     return performMulLoHi24Combine(N, DCI);
   case ISD::SELECT:
     return performSelectCombine(N, DCI);
   case AMDGPUISD::BFE_I32:

llvm/trunk/test/CodeGen/AMDGPU/mad_uint24.ll

entry:
   %0 = ashr i32 %a, 8
   %1 = icmp ne i32 %c, 0
   %2 = select i1 %1, i32 %0, i32 34
   %3 = mul i32 %2, %c
   %4 = add i32 %3, %d
   store i32 %4, i32 addrspace(1)* %out
   ret void
 }
+
+; FUNC-LABEL: {{^}}extra_and:
+; SI-NOT: v_and
+; SI: v_mad_u32_u24
+; SI: v_mad_u32_u24
+define amdgpu_kernel void @extra_and(i32 addrspace(1)* %arg, i32 %arg2, i32 %arg3) {
+bb:
+  br label %bb4
+
+bb4:                                              ; preds = %bb4, %bb
+  %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
+  %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
+  %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
+  %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
+  %tmp8 = and i32 %tmp7, 16777215
+  %tmp9 = and i32 %tmp6, 16777215
+  %tmp10 = and i32 %tmp5, 16777215
+  %tmp11 = and i32 %tmp, 16777215
+  %tmp12 = mul i32 %tmp8, %tmp11
+  %tmp13 = add i32 %arg2, %tmp12
+  %tmp14 = mul i32 %tmp9, %tmp11
+  %tmp15 = add i32 %arg3, %tmp14
+  %tmp16 = add nuw nsw i32 %tmp13, %tmp15
+  %tmp17 = icmp eq i32 %tmp16, 8
+  br i1 %tmp17, label %bb18, label %bb4
+
+bb18:                                             ; preds = %bb4
+  store i32 %tmp16, i32 addrspace(1)* %arg
+  ret void
+}
+
+; FUNC-LABEL: {{^}}dont_remove_shift
+; SI: v_lshr
+; SI: v_mad_u32_u24
+; SI: v_mad_u32_u24
+define amdgpu_kernel void @dont_remove_shift(i32 addrspace(1)* %arg, i32 %arg2, i32 %arg3) {
+bb:
+  br label %bb4
+
+bb4:                                              ; preds = %bb4, %bb
+  %tmp = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
+  %tmp5 = phi i32 [ 0, %bb ], [ %tmp13, %bb4 ]
+  %tmp6 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
+  %tmp7 = phi i32 [ 0, %bb ], [ %tmp15, %bb4 ]
+  %tmp8 = lshr i32 %tmp7, 8
+  %tmp9 = lshr i32 %tmp6, 8
+  %tmp10 = lshr i32 %tmp5, 8
+  %tmp11 = lshr i32 %tmp, 8
+  %tmp12 = mul i32 %tmp8, %tmp11
+  %tmp13 = add i32 %arg2, %tmp12
+  %tmp14 = mul i32 %tmp9, %tmp11
+  %tmp15 = add i32 %arg3, %tmp14
+  %tmp16 = add nuw nsw i32 %tmp13, %tmp15
+  %tmp17 = icmp eq i32 %tmp16, 8
+  br i1 %tmp17, label %bb18, label %bb4
+
+bb18:                                             ; preds = %bb4
+  store i32 %tmp16, i32 addrspace(1)* %arg
+  ret void
+}

llvm/trunk/test/CodeGen/AMDGPU/mul_int24.ll

define void @test_smul24_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
   %shl1.i = shl i32 %b, 8
   %shr2.i = ashr i32 %shl1.i, 8
   %conv3.i = sext i32 %shr2.i to i64
   %mul.i = mul i64 %conv3.i, %conv.i
   store i64 %mul.i, i64 addrspace(1)* %out
   ret void
 }
 
-; FIXME: Should be able to eliminate bfe
 ; FUNC-LABEL: {{^}}test_smul24_i64_square:
 ; GCN: s_load_dword [[A:s[0-9]+]]
-; GCN: s_bfe_i32 [[SEXT:s[0-9]+]], [[A]], 0x180000{{$}}
-; GCN-DAG: v_mul_hi_i32_i24_e64 v{{[0-9]+}}, [[SEXT]], [[SEXT]]
-; GCN-DAG: v_mul_i32_i24_e64 v{{[0-9]+}}, [[SEXT]], [[SEXT]]
+; GCN-DAG: v_mul_hi_i32_i24_e64 v{{[0-9]+}}, [[A]], [[A]]
+; GCN-DAG: v_mul_i32_i24_e64 v{{[0-9]+}}, [[A]], [[A]]
 ; GCN: buffer_store_dwordx2
 define void @test_smul24_i64_square(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
   %shl.i = shl i32 %a, 8
   %shr.i = ashr i32 %shl.i, 8
   %conv.i = sext i32 %shr.i to i64
   %mul.i = mul i64 %conv.i, %conv.i
   store i64 %mul.i, i64 addrspace(1)* %out
   ret void

llvm/trunk/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll

entry:
   %a_24 = lshr i64 %tmp0, 40
   %tmp1 = shl i64 %b, 40
   %b_24 = lshr i64 %tmp1, 40
   %tmp2 = mul i64 %a_24, %b_24
   store i64 %tmp2, i64 addrspace(1)* %out
   ret void
 }
 
-; FIXME: Should be able to eliminate the and.
 ; FUNC-LABEL: {{^}}test_umul24_i64_square:
 ; GCN: s_load_dword [[A:s[0-9]+]]
-; GCN: s_and_b32 [[TRUNC:s[0-9]+]], [[A]], 0xffffff{{$}}
-; GCN-DAG: v_mul_hi_u32_u24_e64 v{{[0-9]+}}, [[TRUNC]], [[TRUNC]]
-; GCN-DAG: v_mul_u32_u24_e64 v{{[0-9]+}}, [[TRUNC]], [[TRUNC]]
+; GCN-NOT: s_and_b32
+; GCN-DAG: v_mul_hi_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
+; GCN-DAG: v_mul_u32_u24_e64 v{{[0-9]+}}, [[A]], [[A]]
 define void @test_umul24_i64_square(i64 addrspace(1)* %out, i64 %a) {
 entry:
   %tmp0 = shl i64 %a, 40
   %a.24 = lshr i64 %tmp0, 40
   %tmp2 = mul i64 %a.24, %a.24
   store i64 %tmp2, i64 addrspace(1)* %out
   ret void
 }