More processors support under AARch64 state for auto detection.

[supra]

Summary

Support for ARMv8-A based APM X-Gene-1 Processor

NEW DIFFERENTIAL REVISION:

1. Adds support for Applied Micro (APM) X-Gene-1 processor.
   • Auto detection (-mcpu=native) under AArch64 state
   • Correct set of pre-defined macros for the features of this model
   • Currently uses "generic" scheduler. Will be enhanced soon.
2. Adds support for ARM Cortex-A53, A57, A72 and A73
   • Auto detection (-mcpu=natie) under AArch64 state

[supra]

Updating D24661: More processors support under AARch64 state for auto detection.
Adding more files to the changeset.

[rengolin]

Those are just the tests, where is the detection code?

[supra]

Adding all the files in the changeset.

(Sorry, not yet well versed with arc)

[t.p.northover]

lib/Support/Host.cpp

1122–1128 ↗

(On Diff #71773)

I don't like how this scales with the many vendors. We'll end up with this loop duplicated half a dozen times before we're done.

Perhaps convert the strings to numbers and use std::lower_bound on a static array?

[rengolin]

lib/Support/Host.cpp

1122–1128 ↗

(On Diff #71773)

Could we maybe add this to the target parser?

[jgreenhalgh]

lib/Target/AArch64/AArch64.td

255

This disagrees with the GCC implementation of -mcpu=xgene1 and the xgene-1 processors available in the GCC compile farm (gcc113.osuosl.org is an APM X-Gene Mustang board). Are you sure that the CRC feature should be enabled?

This comment also applies to the lib/Target/ARM/ARM.td portion of your patch.

[supra]

CRC is not available on APM X-Gene-1. Removed CRC for
-mcpu=xgene1.

[rengolin]

As adding XGene1 goes, the change is reasonable, but there's an auto-detection left-over.

A couple of LLVM-specifics...

• Clang and LLVM are in different repositories, so we'll need two different reviews, one for each part.
• The Clang tests for xgene are good, but we'll also need TargetParser tests (see ./unittests/Support/TargetParserTest.cpp)

A few other comments inline.

Thanks!
--renato

include/llvm/Support/ARMTargetParser.def

237

@jgreenhalgh, is this the same defaults as GCC?

include/llvm/Support/TargetParser.h

165 ↗

(On Diff #72146)

this change now is unnecessary

lib/Support/Host.cpp

1098 ↗

(On Diff #72146)

As discussed over the mailing list, please discard this change.

[jgreenhalgh]

include/llvm/Support/ARMTargetParser.def

237

Yes, the XGene-1 change looks good to me now. Thanks for the update Supra.

[supra]

Removed auto detection for -mcpu=native

[rengolin]

Two small style comments, but it looks good to me with those changes.

Thanks!
--renato

include/llvm/Support/TargetParser.h

165 ↗

(On Diff #72235)

There's no need to keep the comma now that you're not changing the list. Once you do, you can leave another on the new tag.

unittests/Support/TargetParserTest.cpp

549

keep this in the same line, pls.

[supra]

Fixed some coding style issues.

[rengolin]

LGTM, thanks!

[rengolin]

Oh, I just noticed again, sorry (swapping a bit). This code doesn't even compile.

You have three patches here:

1. AArch64 changes, adding XGene1: You need to add the model and descriptions on all related table-gen files. You're defining it but not using it.
2. ARM changes, adding XGene1: You need to define in the same way you did for AArch64, because the usage can't find the declaration, which is in the AArch64.td.
3. Clang changes: the tests rely on the targets being there, so need to be committed *after* the LLVM patch.

For 1 and 2, you'll need two separate patches, with similar changes and appropriate unit tests.

For 3, you'll need both ARM and AArch64 tests (-target armv8a and -target aarch64), and make sure to mention the patch *depends* on the LLVM ones.

Sorry for the confusion, and please, before submitting the three patches, make sure that they build and pass "check-all" individually, as well as altogether.

cheers,
--renato

include/llvm/Support/AArch64TargetParser.def

 AARCH64_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                 (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))
 AARCH64_CPU_NAME("exynos-m2", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                 (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))
 AARCH64_CPU_NAME("kryo", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false,
                 (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))
 AARCH64_CPU_NAME("vulcan", AK_ARMV8_1A, FK_CRYPTO_NEON_FP_ARMV8, false,
                 (AArch64::AEK_SIMD | AArch64::AEK_CRC | AArch64::AEK_CRYPTO))
+AARCH64_CPU_NAME("xgene1", AK_ARMV8A, FK_NEON_FP_ARMV8, false,
+                (AArch64::AEK_SIMD | AArch64::AEK_FP))
 // Invalid CPU
 AARCH64_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, AArch64::AEK_INVALID)
 #undef AARCH64_CPU_NAME

include/llvm/Support/ARMTargetParser.def

 ARM_CPU_NAME("cortex-a35", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cortex-a73", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
 ARM_CPU_NAME("exynos-m2", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, ARM::AEK_CRC)
+ARM_CPU_NAME("xgene1", AK_ARMV8A, FK_NEON_FP_ARMV8, false, 
+  ARM::AEK_FP | ARM::AEK_SIMD)
 // Non-standard Arch names.
 ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("swift", AK_ARMV7S, FK_NEON_VFPV4, true,
              (ARM::AEK_HWDIVARM | ARM::AEK_HWDIV))
 // Invalid CPU
 ARM_CPU_NAME("invalid", AK_INVALID, FK_INVALID, true, ARM::AEK_INVALID)
 #undef ARM_CPU_NAME

lib/Target/AArch64/AArch64.td

def ProcVulcan  : SubtargetFeature<"vulcan", "ARMProcFamily", "Vulcan",
                                    FeatureCrypto,
                                    FeatureFPARMv8,
                                    FeatureMacroOpFusion,
                                    FeatureNEON,
                                    FeaturePostRAScheduler,
                                    FeaturePredictableSelectIsExpensive,
                                    HasV8_1aOps]>;
 
+def ProcXGene1     : SubtargetFeature<"xgene1", "ARMProcFamily", "XGene1",
+                                   "AppliedMicro (APM) X-Gene-1 processors", [
+                                   FeatureFPARMv8,
+                                   FeatureNEON,
+                                   FeaturePerfMon
+                                   ]>;
+
 def : ProcessorModel<"generic", NoSchedModel, [
                      FeatureCRC,
                      FeatureFPARMv8,
                      FeatureNEON,
                      FeaturePerfMon,
                      FeaturePostRAScheduler
                      ]>;
 
 // FIXME: Cortex-A35 is currently modelled as a Cortex-A53
 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 // FIXME: Cortex-A72 and Cortex-A73 are currently modelled as an Cortex-A57.
 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM1]>;
 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 def : ProcessorModel<"vulcan", VulcanModel, [ProcVulcan]>;
+// FIXME: X-Gene-1 is currently modelled as generic schedule.
+def : ProcessorModel<"xgene1", NoSchedModel, [ProcXGene1]>;
 
 //===----------------------------------------------------------------------===//
 // Assembly parser
 //===----------------------------------------------------------------------===//
 
 def GenericAsmParserVariant : AsmParserVariant {
   int Variant = 0;
   string Name = "generic";

lib/Target/AArch64/AArch64Subtarget.h

enum ARMProcFamilyEnum : uint8_t {
     CortexA35,
     CortexA53,
     CortexA57,
     CortexA72,
     CortexA73,
     Cyclone,
     ExynosM1,
     Kryo,
-    Vulcan
+    Vulcan,
+    XGene1
   };
 
 protected:
   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
   ARMProcFamilyEnum ARMProcFamily = Others;
 
   bool HasV8_1aOps = false;
   bool HasV8_2aOps = false;

lib/Target/AArch64/AArch64Subtarget.cpp

case Kryo:
     break;
   case Vulcan:
     MaxInterleaveFactor = 4;
     break;
   case CortexA35: break;
   case CortexA53: break;
   case CortexA72: break;
   case CortexA73: break;
+  case XGene1:    break;
   case Others: break;
   }
 }
 
 AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU,
                                    const std::string &FS,
                                    const TargetMachine &TM, bool LittleEndian)
     : AArch64GenSubtargetInfo(TT, CPU, FS), ReserveX18(TT.isOSDarwin()),

lib/Target/ARM/ARM.td

def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
                                                          FeatureCRC]>;
 
 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
                                                          FeatureHWDiv,
                                                          FeatureHWDivARM,
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
+def : ProcNoItin<"xgene1",                              [ARMv8a, ProcXGene1,
+                                                         FeatureHWDiv,
+                                                         FeatureHWDivARM]>;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
 include "ARMRegisterInfo.td"
 
 include "ARMCallingConv.td"
 

lib/Target/ARM/ARMSubtarget.h

 class ARMBaseTargetMachine;
 
 class ARMSubtarget : public ARMGenSubtargetInfo {
 protected:
   enum ARMProcFamilyEnum {
     Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
     CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexM3,
     CortexA32, CortexA35, CortexA53, CortexA57, CortexA72, CortexA73,
-    Krait, Swift, ExynosM1
+    Krait, Swift, ExynosM1, XGene1
   };
   enum ARMProcClassEnum {
     None, AClass, RClass, MClass
   };
   enum ARMArchEnum {
     ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te,
     ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6t2, ARMv6m, ARMv6sm, ARMv7a, ARMv7r,
     ARMv7m, ARMv7em, ARMv8a, ARMv81a, ARMv82a, ARMv8mMainline, ARMv8mBaseline

lib/Target/ARM/ARMSubtarget.cpp

case CortexA15:
     break;
   case CortexA17:
   case CortexA32:
   case CortexA35:
   case CortexA53:
   case CortexA57:
   case CortexA72:
   case CortexA73:
+  case XGene1:
   case CortexR4:
   case CortexR4F:
   case CortexR5:
   case CortexR7:
   case CortexM3:
   case ExynosM1:
     break;
   case Krait:

tools/clang/test/Driver/aarch64-cpus.c

 
 // RUN: %clang -target aarch64 -mcpu=CORTEX-A57 -### -c %s 2>&1 | FileCheck -check-prefix=CASE-INSENSITIVE-CA57 %s
 // RUN: %clang -target aarch64 -mtune=CORTEX-A57 -### -c %s 2>&1 | FileCheck -check-prefix=CASE-INSENSITIVE-CA57 %s
 // CASE-INSENSITIVE-CA57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a57"
 
 // RUN: %clang -target arm64 -mcpu=Cortex-A57 -### -c %s 2>&1 | FileCheck -check-prefix=CASE-INSENSITIVE-ARM64-CA57 %s
 // RUN: %clang -target arm64 -mtune=Cortex-A57 -### -c %s 2>&1 | FileCheck -check-prefix=CASE-INSENSITIVE-ARM64-CA57 %s
 // CASE-INSENSITIVE-ARM64-CA57: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "cortex-a57"
+
+// RUN: %clang -target aarch64 -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1 %s
+// RUN: %clang -target aarch64 -mlittle-endian -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1 %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1 %s
+// RUN: %clang -target aarch64 -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1 %s
+// RUN: %clang -target aarch64_be -mlittle-endian -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1 %s
+// XGENE1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "xgene1"
+
+// RUN: %clang -target arm64 -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-XGENE1 %s
+// RUN: %clang -target arm64 -mlittle-endian -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-XGENE1 %s
+// RUN: %clang -target arm64 -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-XGENE1 %s
+// RUN: %clang -target arm64 -mlittle-endian -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-XGENE1 %s
+// ARM64-XGENE1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "xgene1"
+
+// RUN: %clang -target aarch64_be -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1-BE %s
+// RUN: %clang -target aarch64_be -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1-BE %s
+// RUN: %clang -target aarch64 -mbig-endian -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1-BE %s
+// RUN: %clang -target aarch64_be -mbig-endian -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=XGENE1-BE %s
+// XGENE1-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "xgene1"
+
+// RUN: %clang -target aarch64 -mcpu=vulcan -mtune=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=MCPU-MTUNE %s
+// RUN: %clang -target aarch64 -mtune=xgene1 -mcpu=vulcan  -### -c %s 2>&1 | FileCheck -check-prefix=MCPU-MTUNE %s
+// MCPU-MTUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "xgene1"
+
+// CASE-INSENSITIVE-XGENE1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "xgene1"
+// CASE-INSENSITIVE-ARM64-XGENE1: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "xgene1"

tools/clang/test/Frontend/aarch64-target-cpu.c

 // Ensure we support the various CPU names.
 //
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cortex-a35 -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cortex-a53 -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cortex-a57 -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cortex-a72 -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cortex-a73 -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu cyclone -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu exynos-m1 -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu generic -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu kryo -verify %s
 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu vulcan -verify %s
+// RUN: %clang_cc1 -triple aarch64-unknown-unknown -target-cpu xgene1 -verify %s
 //
 // expected-no-diagnostics

tools/clang/test/Preprocessor/aarch64-target-features.c

 // RUN: %clang -target aarch64 -mcpu=cortex-a53 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A53 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A57 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A72 %s
 // RUN: %clang -target aarch64 -mcpu=cortex-a73 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-A73 %s
 // RUN: %clang -target aarch64 -mcpu=exynos-m1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s
 // RUN: %clang -target aarch64 -mcpu=exynos-m2 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s
 // RUN: %clang -target aarch64 -mcpu=kryo -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-KRYO %s
 // RUN: %clang -target aarch64 -mcpu=vulcan -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-VULCAN %s
+// RUN: %clang -target aarch64 -mcpu=xgene1 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-XGENE1 %s
 // CHECK-MCPU-CYCLONE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crypto" "-target-feature" "+zcm" "-target-feature" "+zcz"
 // CHECK-MCPU-A35: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A53: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-M1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
 // CHECK-MCPU-VULCAN: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
+// CHECK-MCPU-XGENE1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+fp" "-target-feature" "+simd" "-target-feature" "+neon"
 
 // RUN: %clang -target x86_64-apple-macosx -arch arm64 -### -c %s 2>&1 | FileCheck --check-prefix=CHECK-ARCH-ARM64 %s
 // CHECK-ARCH-ARM64: "-target-cpu" "cyclone" "-target-feature" "+neon" "-target-feature" "+crypto" "-target-feature" "+zcm" "-target-feature" "+zcz"
 
 // RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
 // RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto+fp+simd+crc+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-1 %s
 // RUN: %clang -target aarch64 -march=armv8-a+nofp+nosimd+nocrc+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s
 // RUN: %clang -target aarch64 -march=armv8-a+fp+simd+crc+crypto+nofp+nosimd+nocrc+nocrypto -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MARCH-2 %s

unittests/Support/TargetParserTest.cpp

TEST(TargetParserTest, AArch64parseArchExt) {
   for (unsigned i = 0; i < array_lengthof(ArchExt); i++)
     EXPECT_NE(AArch64::AEK_INVALID, AArch64::parseArchExt(ArchExt[i]));
 }
 
 TEST(TargetParserTest, AArch64parseCPUArch) {
   const char *CPU[] = {"cortex-a35", "cortex-a53", "cortex-a57",
                        "cortex-a72", "cortex-a73", "cyclone",
                        "exynos-m1",  "exynos-m2",  "kryo",
-                       "vulcan"};
+                       "vulcan", "xgene1"};
 
   for (const auto &AArch64CPUName : kAArch64CPUNames)
     EXPECT_TRUE(contains(CPU, AArch64CPUName.Name)
                     ? (static_cast<unsigned>(AArch64::ArchKind::AK_INVALID) !=
                        AArch64::parseCPUArch(AArch64CPUName.Name))
                     : (static_cast<unsigned>(AArch64::ArchKind::AK_INVALID) ==
                        AArch64::parseCPUArch(AArch64CPUName.Name)));
 }
 }