[Sparc][LEON] Erratum fix to replace broken SDIV instruction with SDIVcc.

[lero_chris]

Summary

This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included.

[dcederman]

lib/Target/Sparc/LeonPasses.cpp

300–305 ↗

(On Diff #71618)

SDIVcc modifies the integer condition codes, so if any later instruction depends on the current value of those you might get the wrong result. You probably need to do the switch at an earlier stage to prevent this from happening.

[lero_chris]

Addresses Daniel Cederman's concerns about the integer condition codes potentially being corrupted by marking that the ICC (condition codes) are changed by the SDIV instruction when the erratum fix is switched on. This will prevent the compiler from inserting this instruction in between the condition codes being set and later, being used.

This could be fixed in the front-end of the compiler, but it was difficult to find a working solution in the back-end except for this change.

[efriedma]

HasLeonSdivReplace doesn't actually work the way you want it to: division gets selected manually in SparcDAGToDAGISel::Select (https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Sparc/SparcISelDAGToDAG.cpp#L362), not through a pattern, so the predicate has no effect.

Actually, you should be able to substitute in the correct opcode at that point, instead of fixing up the MachineInstr later.

[lero_chris]

Erratum fixed differently, in line with suggestion by Eli Friedman.

[lero_chris]

Indentation in new code caused by Tab usage fixed and replaced with spaces.

[dcederman]

Earlier you had a unit test for this patch, but it seems to have gone missing in the later updates. Could you add it again?

[lero_chris]

(Re-) added unit test. Added test to ensure this doesn't change behaviour for unaffected processors.

[dcederman]

Looks good to me now.

lib/Target/Sparc/LeonFeatures.td

 //support to casa instruction; for leon3 subtarget only
 def LeonCASA : SubtargetFeature<
   "hasleoncasa", 
   "HasLeonCasa", 
   "true", 
   "Enable CASA instruction for LEON3 and LEON4 processors"
 >;
 
+
+def ReplaceSDIV : SubtargetFeature<
+  "replacesdiv",
+  "PerformSDIVReplace",
+  "true",
+  "AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead"
+>;
+          
 def InsertNOPLoad: SubtargetFeature<
   "insertnopload",
   "InsertNOPLoad",
   "true",
   "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" 
 >;
 
 def FixFSMULD : SubtargetFeature<

lib/Target/Sparc/Sparc.td

 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
                 [FeatureLeon]>;
 
 // LEON 2 FT (AT697E)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697e", LEON2Itineraries,
-                [FeatureLeon, InsertNOPLoad]>;
+                [FeatureLeon, ReplaceSDIV, InsertNOPLoad]>;
 
 // LEON 2 FT (AT697F)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697f", LEON2Itineraries,
                 [FeatureLeon, InsertNOPLoad]>;
 
 
 // LEON 3 FT generic

lib/Target/Sparc/SparcISelDAGToDAG.cpp

if (N->getOpcode() == ISD::SDIV) {
       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
     }
     TopPart = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, SP::Y, TopPart,
                                    SDValue())
                   .getValue(1);
 
     // FIXME: Handle div by immediate.
     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
+    // SDIV is a hardware erratum on some LEON2 processors. Replace it with SDIVcc here.
+    if (((SparcTargetMachine&)TM).getSubtargetImpl()->performSDIVReplace()
+        &&
+        Opcode == SP::SDIVrr) {
+      Opcode = SP::SDIVCCrr;
+    }
     CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
     return;
   }
   case ISD::MULHU:
   case ISD::MULHS: {
     // FIXME: Handle mul by immediate.
     SDValue MulLHS = N->getOperand(0);
     SDValue MulRHS = N->getOperand(1);

lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
 
   // LEON features
   bool HasUmacSmac;
   bool HasLeonCasa;
   bool InsertNOPLoad;
   bool FixFSMULD;
   bool ReplaceFMULS;
   bool FixAllFDIVSQRT;
+  bool PerformSDIVReplace;
 
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
public:
   bool isVIS3() const { return IsVIS3; }
   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
   bool useSoftFloat() const { return UseSoftFloat; }
 
   // Leon options
   bool hasUmacSmac() const { return HasUmacSmac; }
+  bool performSDIVReplace() const { return PerformSDIVReplace; }
   bool hasLeonCasa() const { return HasLeonCasa; }
   bool insertNOPLoad() const { return InsertNOPLoad; }
   bool fixFSMULD() const { return FixFSMULD; }
   bool replaceFMULS() const { return ReplaceFMULS; }
   bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.

lib/Target/Sparc/SparcSubtarget.cpp

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   IsVIS = false;
   HasHardQuad = false;
   UsePopc = false;
   UseSoftFloat = false;
 
   // Leon features
   HasLeonCasa = false;
   HasUmacSmac = false;
+  PerformSDIVReplace = false;
   InsertNOPLoad = false;
   FixFSMULD = false;
   ReplaceFMULS = false;
   FixAllFDIVSQRT = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())

test/CodeGen/SPARC/LeonReplaceSDIVPassUT.ll

+; RUN: llc %s -O0 -march=sparc -o - | FileCheck %s -check-prefix=NO_REPLACE_SDIV
+; RUN: llc %s -O0 -march=sparc -mcpu=at697e -o - | FileCheck %s -check-prefix=REPLACE_SDIV
+
+; REPLACE_SDIV: sdivcc %o0, %o1, %o0
+; NO_REPLACE_SDIV: sdiv %o0, %o1, %o0
+
+define i32 @lbr59(i32 %a, i32 %b)
+{
+  %r = sdiv i32 %a, %b
+  ret i32 %r 
+}