- User Since
- Feb 10 2016, 7:10 AM (196 w, 1 d)
Nov 1 2016
Oct 19 2016
Closed. May make small change as per last comment in a subsequent check-in.
Oct 18 2016
Per comments in review, converted this to detect a rounding change only. It issues an error with a message that this is an erratum on the processor that the user will need to handle in a source code change. The unit test tests that the error message is produced.
Oct 17 2016
Added unit tests which should have been included in the original review.
This review has been separated into seperate reviews. Abandoning this as an open review.
Oct 7 2016
Oct 6 2016
(Re-) added unit test. Added test to ensure this doesn't change behaviour for unaffected processors.
Indentation in new code caused by Tab usage fixed and replaced with spaces.
Erratum fixed differently, in line with suggestion by Eli Friedman.
Oct 5 2016
Addresses Daniel Cederman's concerns about the integer condition codes potentially being corrupted by marking that the ICC (condition codes) are changed by the SDIV instruction when the erratum fix is switched on. This will prevent the compiler from inserting this instruction in between the condition codes being set and later, being used.
Sep 28 2016
If nobody has any comments, I'll check this in tomorrow: 29th Sept, as this has now been on review for two weeks.
Sep 22 2016
Sep 16 2016
Sep 5 2016
Hi, The formatting changes that were *entirely* unrelated to the code updates have been removed. As part of the review process, I also removed all the inline ASM code,m as requested by James Knight. Otherwise, the changes are all specifically to do with the updated passes, except some very small changes to comments and formatting *entirely in and around code that has been changed as part of this update*.
Sep 2 2016
Removed the IgnoreZeroFlag erratum fix pass containing "wr %g0, 1, %psr" as this pass does not have any effect.
Sep 1 2016
Addresses some of the review comments.
Update to reviewed code to address comments.
Aug 12 2016
Removed change to length of supported atomics for LEON processors. Should have always been 32 bit and the previous change wasn't necessary in SparcISelLowering.cpp
Removed RestoreExecAddress and FillDataCache passes as these will have no effect.
We have discussed this with our customers. We have agreed that this pass does not make sense here and we will therefore cancel this change.
Hi Daniel. Nobody was commenting and I need to get this checked-in as I won't be around for three weeks now. You commented at *exactly* the same time as I did the check-in. Otherwise, I had addressed all the review comments.
We were asked to write this optimisation, but we'll revert and ask our customers if they still want this as the point made by James Knight has distinct point. This review may ultimately be cancelled entirely.
Aug 11 2016
Addressing review comments.
Modified some unit tests that were using inline assembler tests to work without this to reflect the non-use of inline assembler in the modified passes.
Added missing unit test and changed command-line invocation. Also added warning message when this optimisation is switched on.
Aug 9 2016
Removed change to CMakeLists.txt that was relevant to a different change and inadvertently added to this review.
Addressing issues in previous review.
Jul 8 2016
Re-opened to address latest comments.
Further updates to address some review comments.
Update to address change recommended by comments. Small formatting changes. Missing unit tests added.
Jul 4 2016
Jul 3 2016
Jun 28 2016
Jun 24 2016
Jun 16 2016
Jun 8 2016
Small change removing unnecessary class qualifier.
Jun 7 2016
Updated code in accordance with feedback.
Jun 3 2016
May 23 2016
Closed and committed after modifications applying to comments and no further activity.
May 20 2016
Micor formatting changes and removal of commented-out code.
- Changes to feature lists on processors to correct mistakes in which processors need errata fixes.
- Changes to getSubtargetImpl to be consistent with the implementation in, e.g. the ARM backend.
May 18 2016
May 16 2016
Tests are working. CASA instruction is available as inline ASM and a small change will allow full atomics behaviour for LEON processors when the AtomicExpandPass is completed.
To avoid regressions in areas of code being worked on by James Knight, I've removed the section of code that will enable atomics for LEON processors.
May 13 2016
Query ability to get this code checked-into the trunk by commenting-out lines that will regress atomics behaviour (temporarily)
May 12 2016
Closing, due to lack on new comments. Changes are working as planned.
May 10 2016
Typos fixed in updated code.
Adjustments in line with comments made.
Combined the two ATOMIC_CMP_SWAP legalisation commands into one.
May 9 2016
Added unit tests covering changing instruction ordering due to different itineraries for LEON processors.
Modified errors in coded unit tests.
May 4 2016
Unit tests to go with this change.
May 3 2016
Made some code modifications, mostly in comments, plus removing redundant code that accidentally made the last check-in.
May 2 2016
Apr 22 2016
Apr 21 2016
Mar 22 2016
Closed, as well embedded into the codebase at this time.
Mar 8 2016
Mar 7 2016
Checked-in as revision 262135
Feb 17 2016
Made amendments following feedback: (1) Added disassembler tests. (2) Moved new FP instruction to correct test file (3) Changed "CoPro" to "Coproc" in both code and filenames. (4) Small white-space formatting changes.
Feb 12 2016
Made modifications to code per comments from jyknight.