[Sparc][LEON] Erratum fix to replace broken SDIV instruction with SDIVcc.

[lero_chris]

Summary

This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included.

[dcederman]

lib/Target/Sparc/LeonPasses.cpp

300–305

SDIVcc modifies the integer condition codes, so if any later instruction depends on the current value of those you might get the wrong result. You probably need to do the switch at an earlier stage to prevent this from happening.

[lero_chris]

Addresses Daniel Cederman's concerns about the integer condition codes potentially being corrupted by marking that the ICC (condition codes) are changed by the SDIV instruction when the erratum fix is switched on. This will prevent the compiler from inserting this instruction in between the condition codes being set and later, being used.

This could be fixed in the front-end of the compiler, but it was difficult to find a working solution in the back-end except for this change.

[efriedma]

HasLeonSdivReplace doesn't actually work the way you want it to: division gets selected manually in SparcDAGToDAGISel::Select (https://github.com/llvm-mirror/llvm/blob/master/lib/Target/Sparc/SparcISelDAGToDAG.cpp#L362), not through a pattern, so the predicate has no effect.

Actually, you should be able to substitute in the correct opcode at that point, instead of fixing up the MachineInstr later.

[lero_chris]

Erratum fixed differently, in line with suggestion by Eli Friedman.

[lero_chris]

Indentation in new code caused by Tab usage fixed and replaced with spaces.

[dcederman]

Earlier you had a unit test for this patch, but it seems to have gone missing in the later updates. Could you add it again?

[lero_chris]

(Re-) added unit test. Added test to ensure this doesn't change behaviour for unaffected processors.

[dcederman]

Looks good to me now.

lib/Target/Sparc/LeonFeatures.td

 //support to casa instruction; for leon3 subtarget only
 def LeonCASA : SubtargetFeature<
   "hasleoncasa", 
   "HasLeonCasa", 
   "true", 
   "Enable CASA instruction for LEON3 and LEON4 processors"
 >;
 
+
+def ReplaceSDIV : SubtargetFeature<
+  "replacesdiv",
+  "PerformSDIVReplace",
+  "true",
+  "AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead"
+>;
+          
 def InsertNOPLoad: SubtargetFeature<
   "insertnopload",
   "InsertNOPLoad",
   "true",
   "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" 
 >;
 
 def FixFSMULD : SubtargetFeature<

lib/Target/Sparc/LeonPasses.h

protected:
   void clearUsedRegisterList() { UsedRegisters.clear(); }
 
   void markRegisterUsed(int registerIndex) {
     UsedRegisters.push_back(registerIndex);
   }
   int getUnusedFPRegister(MachineRegisterInfo &MRI);
 };
 
+class LLVM_LIBRARY_VISIBILITY ReplaceSDIV : public LEONMachineFunctionPass {
+public:
+  static char ID;
+
+  ReplaceSDIV();
+  ReplaceSDIV(TargetMachine &tm);
+  bool runOnMachineFunction(MachineFunction &MF) override;
+
+  StringRef getPassName() const override {
+    return "ReplaceSDIV: Leon erratum fix:  do not emit SDIV, but emit SDIVCC "
+           "instead";
+  }
+};
+
 class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass {
 public:
   static char ID;
 
   InsertNOPLoad(TargetMachine &tm);
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   StringRef getPassName() const override {

lib/Target/Sparc/LeonPasses.cpp

for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
       }
     }
   }
 
   return Modified;
 }
 
 //*****************************************************************************
+//**** ReplaceSDIV pass
+//*****************************************************************************
+// This pass fixes the incorrectly working SDIV instruction that
+// exist for some earlier versions of the LEON processor line. The instruction
+// is replaced with an SDIVcc instruction instead, which is working.
+//
+char ReplaceSDIV::ID = 0;
+
+ReplaceSDIV::ReplaceSDIV() : LEONMachineFunctionPass(ID) {}
+
+ReplaceSDIV::ReplaceSDIV(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {}
+
+bool ReplaceSDIV::runOnMachineFunction(MachineFunction &MF) {
+  Subtarget = &MF.getSubtarget<SparcSubtarget>();
+  const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
+
+  bool Modified = false;
+  for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
+    MachineBasicBlock &MBB = *MFI;
+    for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) {
+      MachineInstr &MI = *MBBI;
+      unsigned Opcode = MI.getOpcode();
+      if (Opcode == SP::SDIVrr) {
+        MI.setDesc(TII.get(SP::SDIVCCrr));
+        Modified = true;
+      } else if (Opcode == SP::SDIVri) {
+        MI.setDesc(TII.get(SP::SDIVCCri));
+        Modified = true;
+      }
+    }
+  }
+
+  return Modified;
+}
+
+//*****************************************************************************
 //**** FixAllFDIVSQRT pass
 //*****************************************************************************
 // This pass fixes the incorrectly working FDIVx and FSQRTx instructions that
 // exist for some earlier versions of the LEON processor line. Five NOP
 // instructions need to be inserted after these instructions to ensure the
 // correct result is placed in the destination registers before they are used.
 //
 // This pass implements two fixes:

lib/Target/Sparc/Sparc.td

 
 // LEON 2 FT generic
 def : Processor<"leon2", LEON2Itineraries,
                 [FeatureLeon]>;
 
 // LEON 2 FT (AT697E)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697e", LEON2Itineraries,
-                [FeatureLeon, InsertNOPLoad]>;
+                [FeatureLeon, ReplaceSDIV, InsertNOPLoad]>;
 
 // LEON 2 FT (AT697F)
 // TO DO: Place-holder: Processor specific features will be added *very* soon here.
 def : Processor<"at697f", LEON2Itineraries,
                 [FeatureLeon, InsertNOPLoad]>;
 
 
 // LEON 3 FT generic

lib/Target/Sparc/SparcISelLowering.cpp

for (MVT VT : MVT::integer_vector_valuetypes()) {
       setTruncStoreAction(VT, MVT::v2i32, Expand);
       setTruncStoreAction(MVT::v2i32, VT, Expand);
     }
     // However, load and store *are* legal.
     setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
     setOperationAction(ISD::STORE, MVT::v2i32, Legal);
     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
     setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
-
     // And we need to promote i64 loads/stores into vector load/store
     setOperationAction(ISD::LOAD, MVT::i64, Custom);
     setOperationAction(ISD::STORE, MVT::i64, Custom);
 
     // Sadly, this doesn't work:
     //    AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32);
     //    AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
   }

lib/Target/Sparc/SparcInstrInfo.td

 // HasUMAC_SMAC - This is true when the target processor supports the
 // UMAC and SMAC instructions
 def HasUMAC_SMAC : Predicate<"Subtarget->hasUmacSmac()">;
 
 def HasNoFdivSqrtFix : Predicate<"!Subtarget->fixAllFDIVSQRT()">;
 def HasNoFmulsFix : Predicate<"!Subtarget->replaceFMULS()">;
 def HasNoFsmuldFix : Predicate<"!Subtarget->fixFSMULD()">;
 
+def HasLeonSdivReplace : Predicate<"Subtarget->performSDIVReplace()">;
+def HasNoLeonSdivReplace : Predicate<"!Subtarget->performSDIVReplace()">;
+
 // UseDeprecatedInsts - This predicate is true when the target processor is a
 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
 // to use when appropriate.  In either of these cases, the instruction selector
 // will pick deprecated instructions.
 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
 
 //===----------------------------------------------------------------------===//
 // Instruction Pattern Stuff
let Defs = [Y, ICC] in {
   defm SMULCC : F3_12np<"smulcc", 0b011011, IIC_iu_smul>;
 }
 
 let Defs = [Y, ICC], Uses = [Y, ICC] in {
   defm MULSCC : F3_12np<"mulscc", 0b100100>;
 }
 
 // Section B.19 - Divide Instructions, p. 115
-let Uses = [Y], Defs = [Y] in {
+let Uses = [Y], Defs = [Y] in 
   defm UDIV : F3_12np<"udiv", 0b001110, IIC_iu_div>;
+  
+let Predicates = [HasNoLeonSdivReplace], Uses = [Y], Defs = [Y] in 
   defm SDIV : F3_12np<"sdiv", 0b001111, IIC_iu_div>;
-}
+
+let Predicates = [HasLeonSdivReplace], DecoderNamespace = "leon2", Uses = [Y], Defs = [Y, ICC] in
+  defm SDIVleon2 : F3_12np<"sdiv", 0b001111, IIC_iu_div>;
 
 let Uses = [Y], Defs = [Y, ICC] in {
   defm UDIVCC : F3_12np<"udivcc", 0b011110, IIC_iu_div>;
   defm SDIVCC : F3_12np<"sdivcc", 0b011111, IIC_iu_div>;
 }
 
 // Section B.20 - SAVE and RESTORE, p. 117
 defm SAVE    : F3_12np<"save"   , 0b111100>;

lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
 
   // LEON features
   bool HasUmacSmac;
   bool HasLeonCasa;
   bool InsertNOPLoad;
   bool FixFSMULD;
   bool ReplaceFMULS;
   bool FixAllFDIVSQRT;
+  bool PerformSDIVReplace;
 
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
public:
   bool isVIS3() const { return IsVIS3; }
   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
   bool useSoftFloat() const { return UseSoftFloat; }
 
   // Leon options
   bool hasUmacSmac() const { return HasUmacSmac; }
+  bool performSDIVReplace() const { return PerformSDIVReplace; }
   bool hasLeonCasa() const { return HasLeonCasa; }
   bool insertNOPLoad() const { return InsertNOPLoad; }
   bool fixFSMULD() const { return FixFSMULD; }
   bool replaceFMULS() const { return ReplaceFMULS; }
   bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.

lib/Target/Sparc/SparcSubtarget.cpp

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
   IsVIS = false;
   HasHardQuad = false;
   UsePopc = false;
   UseSoftFloat = false;
 
   // Leon features
   HasLeonCasa = false;
   HasUmacSmac = false;
+  PerformSDIVReplace = false;
   InsertNOPLoad = false;
   FixFSMULD = false;
   ReplaceFMULS = false;
   FixAllFDIVSQRT = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())

lib/Target/Sparc/SparcTargetMachine.cpp

 bool SparcPassConfig::addInstSelector() {
   addPass(createSparcISelDag(getSparcTargetMachine()));
   return false;
 }
 
 void SparcPassConfig::addPreEmitPass(){
   addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
 
+  if (this->getSparcTargetMachine().getSubtargetImpl()->performSDIVReplace()) {
+    addPass(new ReplaceSDIV(getSparcTargetMachine()));
+  }
   if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad())
   {
     addPass(new InsertNOPLoad(getSparcTargetMachine()));
   }
   if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD())
   {
     addPass(new FixFSMULD(getSparcTargetMachine()));
   }