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Differential D23996

[AMDGPU] refactor SMRD/SMEM TD instruction definitions
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Authored by vpykhtin on Aug 29 2016, 10:13 AM.

Details

Reviewers
artem.tamazov
• tstellarAMD
arsenm
SamWot
Commits
rG1b13886b5f62: [AMDGPU] Scalar Memory instructions TD refactoring
rL280349: [AMDGPU] Scalar Memory instructions TD refactoring

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Event Timeline

vpykhtin updated this revision to Diff 69577.Aug 29 2016, 10:13 AM
vpykhtin retitled this revision from to [AMDGPU] refactor SMRD/SMEM TD instruction definitions.
vpykhtin updated this object.
vpykhtin added reviewers: arsenm, • tstellarAMD, artem.tamazov, SamWot.
vpykhtin set the repository for this revision to rL LLVM.
vpykhtin added a project: Restricted Project.
vpykhtin added a subscriber: nhaustov.
Herald added subscribers: kzhuravl, arsenm. · View Herald TranscriptAug 29 2016, 10:13 AM
artem.tamazov accepted this revision.Aug 30 2016, 2:46 AM
artem.tamazov edited edge metadata.

Looks good. Please run lit tests used for weekly testing (see AMDGPU asm weekly report) and go ahead if no regressions.

This revision is now accepted and ready to land.Aug 30 2016, 2:46 AM
vpykhtin updated this revision to Diff 69828.Aug 31 2016, 4:55 AM
vpykhtin edited edge metadata.
vpykhtin removed rL LLVM as the repository for this revision.

updated diff after SOP commit.

Herald added a subscriber: wdng. · View Herald TranscriptAug 31 2016, 4:55 AM
vpykhtin added a comment.Aug 31 2016, 4:56 AM

Lit testing passed.

• tstellarAMD accepted this revision.Aug 31 2016, 1:21 PM
• tstellarAMD edited edge metadata.

OCL/OGL tests pass. LGTM.

Closed by commit rL280349: [AMDGPU] Scalar Memory instructions TD refactoring (authored by vpykhtin). · Explain WhySep 1 2016, 3:05 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
8 lines
54 lines
177 lines
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Diff 69828

lib/Target/AMDGPU/CIInstructions.td

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
>; >;
// XXX - Does this set VCC? // XXX - Does this set VCC?
defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32", defm V_MAD_I64_I32 : VOP3Inst <vop3<0x177>, "v_mad_i64_i32",
VOP_I64_I32_I32_I64 VOP_I64_I32_I32_I64
>; >;
} // End isCommutable = 1 } // End isCommutable = 1
//===----------------------------------------------------------------------===//
// SMRD Instructions
//===----------------------------------------------------------------------===//
defm S_DCACHE_INV_VOL : SMRD_Inval <smrd<0x1d, 0x22>,
"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// MUBUF Instructions // MUBUF Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let DisableSIDecoder = 1 in { let DisableSIDecoder = 1 in {
defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>, defm BUFFER_WBINVL1_VOL : MUBUF_Invalidate <mubuf<0x70, 0x3f>,
"buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol "buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol
>; >;
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lib/Target/AMDGPU/SIInstrFormats.td

Show First 20 Lines • Show All 194 Lines • ▼ Show 20 Linesclass VOP3Common <dag outs, dag ins, string asm = "",
// need a post-isel hook to insert copies in order to avoid // need a post-isel hook to insert copies in order to avoid
// violating constant bus requirements. // violating constant bus requirements.
let hasPostISelHook = 1; let hasPostISelHook = 1;
} }
} // End Uses = [EXEC] } // End Uses = [EXEC]
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scalar operations
//===----------------------------------------------------------------------===//
class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
bits<7> sdst;
bits<7> sbase;
let Inst{8} = imm;
let Inst{14-9} = sbase{6-1};
let Inst{21-15} = sdst;
let Inst{26-22} = op;
let Inst{31-27} = 0x18; //encoding
}
class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> {
bits<8> offset;
let Inst{7-0} = offset;
}
class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> {
bits<8> soff;
let Inst{7-0} = soff;
}
class SMRD_IMMe_ci <bits<5> op> : Enc64 {
bits<7> sdst;
bits<7> sbase;
bits<32> offset;
let Inst{7-0} = 0xff;
let Inst{8} = 0;
let Inst{14-9} = sbase{6-1};
let Inst{21-15} = sdst;
let Inst{26-22} = op;
let Inst{31-27} = 0x18; //encoding
let Inst{63-32} = offset;
}
class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI<outs, ins, asm, pattern> {
let LGKM_CNT = 1;
let SMRD = 1;
let mayStore = 0;
let mayLoad = 1;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let SchedRW = [WriteSMEM];
}
//===----------------------------------------------------------------------===//
// Vector ALU operations // Vector ALU operations
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class VOP1e <bits<8> op> : Enc32 { class VOP1e <bits<8> op> : Enc32 {
bits<8> vdst; bits<8> vdst;
bits<9> src0; bits<9> src0;
let Inst{8-0} = src0; let Inst{8-0} = src0;
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lib/Target/AMDGPU/SIInstrInfo.td

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Linesclass vop23 <bits<6> si, bits<10> vi> : vop2 <si> {
let VI3 = vi; let VI3 = vi;
} }
class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop { class vop3 <bits<9> si, bits<10> vi = {0, si}> : vop {
let SI3 = si; let SI3 = si;
let VI3 = vi; let VI3 = vi;
} }
// Specify an SMRD opcode for SI and SMEM opcode for VI
// FIXME: This should really be bits<5> si, Tablegen crashes if
// parameter default value is other parameter with different bit size
class smrd<bits<8> si, bits<8> vi = si> {
field bits<5> SI = si{4-0};
field bits<8> VI = vi;
}
// Execpt for the NONE field, this must be kept in sync with the // Execpt for the NONE field, this must be kept in sync with the
// SIEncodingFamily enum in AMDGPUInstrInfo.cpp // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
def SIEncodingFamily { def SIEncodingFamily {
int NONE = -1; int NONE = -1;
int SI = 0; int SI = 0;
int VI = 1; int VI = 1;
} }
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def mubuf_load : MubufLoad <load>; def mubuf_load : MubufLoad <load>;
def mubuf_az_extloadi8 : MubufLoad <az_extloadi8>; def mubuf_az_extloadi8 : MubufLoad <az_extloadi8>;
def mubuf_sextloadi8 : MubufLoad <sextloadi8>; def mubuf_sextloadi8 : MubufLoad <sextloadi8>;
def mubuf_az_extloadi16 : MubufLoad <az_extloadi16>; def mubuf_az_extloadi16 : MubufLoad <az_extloadi16>;
def mubuf_sextloadi16 : MubufLoad <sextloadi16>; def mubuf_sextloadi16 : MubufLoad <sextloadi16>;
def mubuf_load_atomic : MubufLoad <atomic_load>; def mubuf_load_atomic : MubufLoad <atomic_load>;
def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
auto Ld = cast<LoadSDNode>(N);
return Ld->getAlignment() >= 4 &&
Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);
}]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// PatFrags for global memory operations // PatFrags for global memory operations
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def atomic_inc_global : global_binary_atomic_op<SIatomic_inc>; def atomic_inc_global : global_binary_atomic_op<SIatomic_inc>;
def atomic_dec_global : global_binary_atomic_op<SIatomic_dec>; def atomic_dec_global : global_binary_atomic_op<SIatomic_dec>;
def atomic_inc_flat : flat_binary_atomic_op<SIatomic_inc>; def atomic_inc_flat : flat_binary_atomic_op<SIatomic_inc>;
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def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>; def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>; def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>; def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>; def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>; def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
def smrd_offset : NamedOperandU32<"SMRDOffset", NamedMatchClass<"SMRDOffset">>;
def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset", NamedMatchClass<"SMRDLiteralOffset">>;
def glc : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>; def glc : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>; def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>; def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>; def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>; def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>; def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>; def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
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def FLATAtomic : ComplexPattern<i64, 3, "SelectFlat">; def FLATAtomic : ComplexPattern<i64, 3, "SelectFlat">;
def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">; def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">; def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">; def MUBUFOffsetNoGLC : ComplexPattern<i64, 3, "SelectMUBUFOffset">;
def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">; def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
def MUBUFIntrinsicOffset : ComplexPattern<i32, 2, "SelectMUBUFIntrinsicOffset">; def MUBUFIntrinsicOffset : ComplexPattern<i32, 2, "SelectMUBUFIntrinsicOffset">;
def MUBUFIntrinsicVOffset : ComplexPattern<i32, 3, "SelectMUBUFIntrinsicVOffset">; def MUBUFIntrinsicVOffset : ComplexPattern<i32, 3, "SelectMUBUFIntrinsicVOffset">;
def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">; def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">; def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">; def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">; def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">; def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">; def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">; def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linesmulticlass EXP_m {
def _vi : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.VI>, EXPe_vi { def _vi : EXPCommon, SIMCInstr <"exp", SIEncodingFamily.VI>, EXPe_vi {
let DecoderNamespace="VI"; let DecoderNamespace="VI";
let DisableDecoder = DisableVIDecoder; let DisableDecoder = DisableVIDecoder;
} }
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Scalar classes
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// SMRD classes
//===----------------------------------------------------------------------===//
class SMRD_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
SMRD <outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
}
class SMRD_IMM_Real_si <bits<5> op, string opName, dag outs, dag ins,
string asm> :
SMRD <outs, ins, asm, []>,
SMRD_IMMe <op>,
SIMCInstr<opName, SIEncodingFamily.SI> {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
class SMRD_SOFF_Real_si <bits<5> op, string opName, dag outs, dag ins,
string asm> :
SMRD <outs, ins, asm, []>,
SMRD_SOFFe <op>,
SIMCInstr<opName, SIEncodingFamily.SI> {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let DisableDecoder = DisableSIDecoder;
}
class SMRD_IMM_Real_vi <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pattern = []> :
SMRD <outs, ins, asm, pattern>,
SMEM_IMMe_vi <op>,
SIMCInstr<opName, SIEncodingFamily.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
class SMRD_SOFF_Real_vi <bits<8> op, string opName, dag outs, dag ins,
string asm, list<dag> pattern = []> :
SMRD <outs, ins, asm, pattern>,
SMEM_SOFFe_vi <op>,
SIMCInstr<opName, SIEncodingFamily.VI> {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let DisableDecoder = DisableVIDecoder;
}
multiclass SMRD_IMM_m <smrd op, string opName, dag outs, dag ins,
string asm, list<dag> pattern> {
def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
def _si : SMRD_IMM_Real_si <op.SI, opName, outs, ins, asm>;
// glc is only applicable to scalar stores, which are not yet
// implemented.
let glc = 0 in {
def _vi : SMRD_IMM_Real_vi <op.VI, opName, outs, ins, asm>;
}
}
multiclass SMRD_SOFF_m <smrd op, string opName, dag outs, dag ins,
string asm, list<dag> pattern> {
def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, ins, asm>;
// glc is only applicable to scalar stores, which are not yet
// implemented.
let glc = 0 in {
def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, ins, asm>;
}
}
multiclass SMRD_Special <smrd op, string opName, dag outs,
int sdst_ = ?,
string opStr = "",
list<dag> pattern = []> {
let hasSideEffects = 1 in {
def "" : SMRD_Pseudo <opName, outs, (ins), pattern>;
let sbase = 0, soff = 0, sdst = sdst_ in {
def _si : SMRD_SOFF_Real_si <op.SI, opName, outs, (ins), opName#opStr>;
let glc = 0 in {
def _vi : SMRD_SOFF_Real_vi <op.VI, opName, outs, (ins), opName#opStr>;
}
}
}
}
multiclass SMRD_Inval <smrd op, string opName,
SDPatternOperator node> {
let mayStore = 1 in {
defm : SMRD_Special<op, opName, (outs), 0, "", [(node)]>;
}
}
class SMEM_Inval <bits<8> op, string opName, SDPatternOperator node> :
SMRD_SOFF_Real_vi<op, opName, (outs), (ins), opName, [(node)]> {
let hasSideEffects = 1;
let mayStore = 1;
let sbase = 0;
let sdst = 0;
let glc = 0;
let soff = 0;
}
class SMEM_Ret <bits<8> op, string opName, SDPatternOperator node> :
SMRD_SOFF_Real_vi<op, opName, (outs SReg_64:$sdst), (ins),
opName#" $sdst", [(set i64:$sdst, (node))]> {
let hasSideEffects = 1;
let mayStore = ?;
let mayLoad = ?;
let sbase = 0;
let glc = 0;
let soff = 0;
}
multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
RegisterClass dstClass> {
defm _IMM : SMRD_IMM_m <
op, opName#"_IMM", (outs dstClass:$sdst),
(ins baseClass:$sbase, smrd_offset:$offset),
opName#" $sdst, $sbase, $offset", []
>;
def _IMM_ci : SMRD <
(outs dstClass:$sdst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
opName#" $sdst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
}
defm _SGPR : SMRD_SOFF_m <
op, opName#"_SGPR", (outs dstClass:$sdst),
(ins baseClass:$sbase, SReg_32:$soff),
opName#" $sdst, $sbase, $soff", []
>;
}
//===----------------------------------------------------------------------===//
// Vector ALU classes // Vector ALU classes
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> { class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
int ret = int ret =
!if (!eq(Src0.Value, untyped.Value), 0, !if (!eq(Src0.Value, untyped.Value), 0,
!if (!eq(Src1.Value, untyped.Value), 1, // VOP1 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
!if (!eq(Src2.Value, untyped.Value), 2, // VOP2 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
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lib/Target/AMDGPU/SIInstructions.td

Show All 16 Lines
def isSI : Predicate<"Subtarget->getGeneration() " def isSI : Predicate<"Subtarget->getGeneration() "
"== SISubtarget::SOUTHERN_ISLANDS">, "== SISubtarget::SOUTHERN_ISLANDS">,
AssemblerPredicate<"FeatureSouthernIslands">; AssemblerPredicate<"FeatureSouthernIslands">;
def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">;
def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">;
include "SOPInstructions.td" include "SOPInstructions.td"
include "SMInstructions.td"
let SubtargetPredicate = isGCN in { let SubtargetPredicate = isGCN in {
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// EXP Instructions // EXP Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm EXP : EXP_m; defm EXP : EXP_m;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SMRD Instructions
//===----------------------------------------------------------------------===//
// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
// SMRD instructions, because the SReg_32_XM0 register class does not include M0
// and writing to M0 from an SMRD instruction will hang the GPU.
defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SReg_32_XM0>;
defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;
defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;
defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;
defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
smrd<0x08>, "s_buffer_load_dword", SReg_128, SReg_32_XM0
>;
defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64
>;
defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128
>;
defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256
>;
defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512
>;
let mayStore = ? in {
// FIXME: mayStore = ? is a workaround for tablegen bug for different
// inferred mayStore flags for the instruction pattern vs. standalone
// Pat. Each considers the other contradictory.
defm S_MEMTIME : SMRD_Special <smrd<0x1e, 0x24>, "s_memtime",
(outs SReg_64:$sdst), ?, " $sdst", [(set i64:$sdst, (int_amdgcn_s_memtime))]
>;
}
defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv",
int_amdgcn_s_dcache_inv>;
//===----------------------------------------------------------------------===//
// VOPC Instructions // VOPC Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let isCompare = 1, isCommutable = 1 in { let isCompare = 1, isCommutable = 1 in {
defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">; defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">;
defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">;
defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>; defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>;
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def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>; def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>;
def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>; def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>;
def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>; def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>;
def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>; def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>;
def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>; def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>;
def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>; def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>;
def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>; def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>;
// SMRD Patterns
//===----------------------------------------------------------------------===//
multiclass SMRD_Pattern <string Instr, ValueType vt> {
// 1. IMM offset
def : Pat <
(smrd_load (SMRDImm i64:$sbase, i32:$offset)),
(vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset))
>;
// 2. SGPR offset
def : Pat <
(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
(vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset))
>;
def : Pat <
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
(vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset))
> {
let Predicates = [isCIOnly];
}
}
// Global and constant loads can be selected to either MUBUF or SMRD
// instructions, but SMRD instructions are faster so we want the instruction
// selector to prefer those.
let AddedComplexity = 100 in {
defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
// 1. Offset as an immediate
def : Pat <
(SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
(S_BUFFER_LOAD_DWORD_IMM $sbase, $offset)
>;
// 2. Offset loaded in an 32bit SGPR
def : Pat <
(SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
>;
let Predicates = [isCI] in {
def : Pat <
(SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)
>;
} // End Predicates = [isCI]
} // End let AddedComplexity = 10000
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VOP1 Patterns // VOP1 Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [UnsafeFPMath] in { let Predicates = [UnsafeFPMath] in {
//def : RcpPat<V_RCP_F64_e32, f64>; //def : RcpPat<V_RCP_F64_e32, f64>;
▲ Show 20 Lines • Show All 1,083 Lines • ▼ Show 20 Linesmulticlass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> {
>; >;
} }
defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>; defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>; // FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
def : BFEPattern <V_BFE_U32, S_MOV_B32>; def : BFEPattern <V_BFE_U32, S_MOV_B32>;
let Predicates = [isSICI] in {
def : Pat <
(i64 (readcyclecounter)),
(S_MEMTIME)
>;
}
def : Pat< def : Pat<
(fcanonicalize f32:$src), (fcanonicalize f32:$src),
(V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0) (V_MUL_F32_e64 0, CONST.FP32_ONE, 0, $src, 0, 0)
>; >;
def : Pat< def : Pat<
(fcanonicalize f64:$src), (fcanonicalize f64:$src),
(V_MUL_F64 0, CONST.FP64_ONE, 0, $src, 0, 0) (V_MUL_F64 0, CONST.FP64_ONE, 0, $src, 0, 0)
▲ Show 20 Lines • Show All 53 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SMInstructions.td

  • This file was added.
//===---- SMInstructions.td - Scalar Memory Instruction Defintions --------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
def smrd_offset : NamedOperandU32<"SMRDOffset",
NamedMatchClass<"SMRDOffset">> {
let OperandType = "OPERAND_IMMEDIATE";
}
//===----------------------------------------------------------------------===//
// Scalar Memory classes
//===----------------------------------------------------------------------===//
class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
InstSI <outs, ins, "", pattern>,
SIMCInstr<opName, SIEncodingFamily.NONE> {
let isPseudo = 1;
let isCodeGenOnly = 1;
let LGKM_CNT = 1;
let SMRD = 1;
let mayStore = 0;
let mayLoad = 1;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let SchedRW = [WriteSMEM];
let SubtargetPredicate = isGCN;
string Mnemonic = opName;
string AsmOperands = asmOps;
bits<1> has_sbase = 1;
bits<1> has_sdst = 1;
bits<1> has_offset = 1;
bits<1> offset_is_imm = 0;
}
class SM_Real <SM_Pseudo ps>
: InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
let isPseudo = 0;
let isCodeGenOnly = 0;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
// encoding
bits<7> sbase;
bits<7> sdst;
bits<32> offset;
bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
}
class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
: SM_Pseudo<opName, outs, ins, asmOps, pattern> {
RegisterClass BaseClass;
}
multiclass SM_Pseudo_Loads<string opName,
RegisterClass baseClass,
RegisterClass dstClass> {
def _IMM : SM_Load_Pseudo <opName,
(outs dstClass:$sdst),
(ins baseClass:$sbase, i32imm:$offset),
" $sdst, $sbase, $offset", []> {
let offset_is_imm = 1;
let BaseClass = baseClass;
let PseudoInstr = opName # "_IMM";
}
def _SGPR : SM_Load_Pseudo <opName,
(outs dstClass:$sdst),
(ins baseClass:$sbase, SReg_32:$soff),
" $sdst, $sbase, $offset", []> {
let BaseClass = baseClass;
let PseudoInstr = opName # "_SGPR";
}
}
class SM_Time_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
opName, (outs SReg_64:$sdst), (ins),
" $sdst", [(set i64:$sdst, (node))]> {
let hasSideEffects = 1;
// FIXME: mayStore = ? is a workaround for tablegen bug for different
// inferred mayStore flags for the instruction pattern vs. standalone
// Pat. Each considers the other contradictory.
let mayStore = ?;
let mayLoad = ?;
let has_sbase = 0;
let has_offset = 0;
}
class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo<
opName, (outs), (ins), "", [(node)]> {
let hasSideEffects = 1;
let mayStore = 1;
let has_sdst = 0;
let has_sbase = 0;
let has_offset = 0;
}
//===----------------------------------------------------------------------===//
// Scalar Memory Instructions
//===----------------------------------------------------------------------===//
// We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
// SMRD instructions, because the SReg_32_XM0 register class does not include M0
// and writing to M0 from an SMRD instruction will hang the GPU.
defm S_LOAD_DWORD : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0>;
defm S_LOAD_DWORDX2 : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64>;
defm S_LOAD_DWORDX4 : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>;
defm S_LOAD_DWORDX8 : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>;
defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>;
defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads <
"s_buffer_load_dword", SReg_128, SReg_32_XM0
>;
defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads <
"s_buffer_load_dwordx2", SReg_128, SReg_64
>;
defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <
"s_buffer_load_dwordx4", SReg_128, SReg_128
>;
defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <
"s_buffer_load_dwordx8", SReg_128, SReg_256
>;
defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <
"s_buffer_load_dwordx16", SReg_128, SReg_512
>;
def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
let SubtargetPredicate = isCIVI in {
def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
} // let SubtargetPredicate = isCIVI
let SubtargetPredicate = isVI in {
def S_DCACHE_WB : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
def S_MEMREALTIME : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
} // SubtargetPredicate = isVI
//===----------------------------------------------------------------------===//
// Scalar Memory Patterns
//===----------------------------------------------------------------------===//
def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
auto Ld = cast<LoadSDNode>(N);
return Ld->getAlignment() >= 4 &&
Ld->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N);
}]>;
def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">;
def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
let Predicates = [isGCN] in {
multiclass SMRD_Pattern <string Instr, ValueType vt> {
// 1. IMM offset
def : Pat <
(smrd_load (SMRDImm i64:$sbase, i32:$offset)),
(vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset))
>;
// 2. SGPR offset
def : Pat <
(smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
(vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset))
>;
}
let Predicates = [isSICI] in {
def : Pat <
(i64 (readcyclecounter)),
(S_MEMTIME)
>;
}
// Global and constant loads can be selected to either MUBUF or SMRD
// instructions, but SMRD instructions are faster so we want the instruction
// selector to prefer those.
let AddedComplexity = 100 in {
defm : SMRD_Pattern <"S_LOAD_DWORD", i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>;
defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
// 1. Offset as an immediate
def SM_LOAD_PATTERN : Pat < // name this pattern to reuse AddedComplexity on CI
(SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
(S_BUFFER_LOAD_DWORD_IMM $sbase, $offset)
>;
// 2. Offset loaded in an 32bit SGPR
def : Pat <
(SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
>;
} // End let AddedComplexity = 100
} // let Predicates = [isGCN]
let Predicates = [isVI] in {
// 1. Offset as 20bit DWORD immediate
def : Pat <
(SIload_constant v4i32:$sbase, IMM20bit:$offset),
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
>;
def : Pat <
(i64 (readcyclecounter)),
(S_MEMREALTIME)
>;
} // let Predicates = [isVI]
//===----------------------------------------------------------------------===//
// Targets
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// SI
//===----------------------------------------------------------------------===//
class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
: SM_Real<ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
, Enc32 {
let AssemblerPredicates = [isSICI];
let DecoderNamespace = "SICI";
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
let Inst{8} = imm;
let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
let Inst{26-22} = op;
let Inst{31-27} = 0x18; //encoding
}
multiclass SM_Real_Loads_si<bits<5> op, string ps,
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
def _IMM_si : SMRD_Real_si <op, immPs> {
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset:$offset);
}
def _SGPR_si : SMRD_Real_si <op, sgprPs> {
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset);
}
}
defm S_LOAD_DWORD : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
defm S_LOAD_DWORDX2 : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
defm S_LOAD_DWORDX4 : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
defm S_LOAD_DWORDX8 : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
defm S_LOAD_DWORDX16 : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">;
defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">;
defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">;
defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">;
defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">;
defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">;
def S_MEMTIME_si : SMRD_Real_si <0x1e, S_MEMTIME>;
def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>;
//===----------------------------------------------------------------------===//
// VI
//===----------------------------------------------------------------------===//
class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
: SM_Real<ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
, Enc64 {
let AssemblerPredicates = [isVI];
let DecoderNamespace = "VI";
let Inst{5-0} = !if(ps.has_sbase, sbase{6-1}, ?);
let Inst{12-6} = !if(ps.has_sdst, sdst{6-0}, ?);
// glc is only applicable to scalar stores, which are not yet
// implemented.
let Inst{16} = 0; // glc bit
let Inst{17} = imm;
let Inst{25-18} = op;
let Inst{31-26} = 0x30; //encoding
let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?);
}
multiclass SM_Real_Loads_vi<bits<8> op, string ps,
SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
def _IMM_vi : SMEM_Real_vi <op, immPs> {
let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset:$offset);
}
def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset);
}
}
defm S_LOAD_DWORD : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
defm S_LOAD_DWORDX2 : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;
defm S_LOAD_DWORDX4 : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">;
defm S_LOAD_DWORDX8 : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">;
defm S_LOAD_DWORDX16 : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">;
defm S_BUFFER_LOAD_DWORD : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">;
defm S_BUFFER_LOAD_DWORDX2 : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">;
defm S_BUFFER_LOAD_DWORDX4 : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">;
defm S_BUFFER_LOAD_DWORDX8 : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">;
defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">;
def S_DCACHE_INV_vi : SMEM_Real_vi <0x20, S_DCACHE_INV>;
def S_DCACHE_WB_vi : SMEM_Real_vi <0x21, S_DCACHE_WB>;
def S_DCACHE_INV_VOL_vi : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
def S_DCACHE_WB_VOL_vi : SMEM_Real_vi <0x23, S_DCACHE_WB_VOL>;
def S_MEMTIME_vi : SMEM_Real_vi <0x24, S_MEMTIME>;
def S_MEMREALTIME_vi : SMEM_Real_vi <0x25, S_MEMREALTIME>;
//===----------------------------------------------------------------------===//
// CI
//===----------------------------------------------------------------------===//
def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
NamedMatchClass<"SMRDLiteralOffset">> {
let OperandType = "OPERAND_IMMEDIATE";
}
class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
SM_Real<ps>,
Enc64 {
let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset);
let LGKM_CNT = ps.LGKM_CNT;
let SMRD = ps.SMRD;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let hasSideEffects = ps.hasSideEffects;
let SchedRW = ps.SchedRW;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Inst{7-0} = 0xff;
let Inst{8} = 0;
let Inst{14-9} = sbase{6-1};
let Inst{21-15} = sdst{6-0};
let Inst{26-22} = op;
let Inst{31-27} = 0x18; //encoding
let Inst{63-32} = offset{31-0};
}
def S_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x00, S_LOAD_DWORD_IMM>;
def S_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x01, S_LOAD_DWORDX2_IMM>;
def S_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x02, S_LOAD_DWORDX4_IMM>;
def S_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x03, S_LOAD_DWORDX8_IMM>;
def S_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x04, S_LOAD_DWORDX16_IMM>;
def S_BUFFER_LOAD_DWORD_IMM_ci : SMRD_Real_Load_IMM_ci <0x08, S_BUFFER_LOAD_DWORD_IMM>;
def S_BUFFER_LOAD_DWORDX2_IMM_ci : SMRD_Real_Load_IMM_ci <0x09, S_BUFFER_LOAD_DWORDX2_IMM>;
def S_BUFFER_LOAD_DWORDX4_IMM_ci : SMRD_Real_Load_IMM_ci <0x0a, S_BUFFER_LOAD_DWORDX4_IMM>;
def S_BUFFER_LOAD_DWORDX8_IMM_ci : SMRD_Real_Load_IMM_ci <0x0b, S_BUFFER_LOAD_DWORDX8_IMM>;
def S_BUFFER_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x0c, S_BUFFER_LOAD_DWORDX16_IMM>;
class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
: SM_Real<ps>
, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
, Enc32 {
let AssemblerPredicates = [isCIOnly];
let DecoderNamespace = "CI";
let Inst{7-0} = !if(ps.has_offset, offset{7-0}, ?);
let Inst{8} = imm;
let Inst{14-9} = !if(ps.has_sbase, sbase{6-1}, ?);
let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
let Inst{26-22} = op;
let Inst{31-27} = 0x18; //encoding
}
def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in {
class SMRD_Pattern_ci <string Instr, ValueType vt> : Pat <
(smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
(vt (!cast<SM_Pseudo>(Instr#"_IMM_ci") $sbase, $offset))> {
let Predicates = [isCIOnly];
}
def : SMRD_Pattern_ci <"S_LOAD_DWORD", i32>;
def : SMRD_Pattern_ci <"S_LOAD_DWORDX2", v2i32>;
def : SMRD_Pattern_ci <"S_LOAD_DWORDX4", v4i32>;
def : SMRD_Pattern_ci <"S_LOAD_DWORDX8", v8i32>;
def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>;
def : Pat <
(SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
(S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset)> {
let Predicates = [isCI]; // should this be isCIOnly?
}
} // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity

lib/Target/AMDGPU/VIInstrFormats.td

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Linesclass MTBUFe_vi <bits<4> op> : Enc64 {
let Inst{39-32} = vaddr; let Inst{39-32} = vaddr;
let Inst{47-40} = vdata; let Inst{47-40} = vdata;
let Inst{52-48} = srsrc{6-2}; let Inst{52-48} = srsrc{6-2};
let Inst{54} = slc; let Inst{54} = slc;
let Inst{55} = tfe; let Inst{55} = tfe;
let Inst{63-56} = soffset; let Inst{63-56} = soffset;
} }
class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
bits<7> sbase;
bits<7> sdst;
bits<1> glc;
let Inst{5-0} = sbase{6-1};
let Inst{12-6} = sdst;
let Inst{16} = glc;
let Inst{17} = imm;
let Inst{25-18} = op;
let Inst{31-26} = 0x30; //encoding
}
class SMEM_IMMe_vi <bits<8> op> : SMEMe_vi<op, 1> {
bits<20> offset;
let Inst{51-32} = offset;
}
class SMEM_SOFFe_vi <bits<8> op> : SMEMe_vi<op, 0> {
bits<20> soff;
let Inst{51-32} = soff;
}
class VOP3a_vi <bits<10> op> : Enc64 { class VOP3a_vi <bits<10> op> : Enc64 {
bits<2> src0_modifiers; bits<2> src0_modifiers;
bits<9> src0; bits<9> src0;
bits<2> src1_modifiers; bits<2> src1_modifiers;
bits<9> src1; bits<9> src1;
bits<2> src2_modifiers; bits<2> src2_modifiers;
bits<9> src2; bits<9> src2;
bits<1> clamp; bits<1> clamp;
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lib/Target/AMDGPU/VIInstructions.td

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} }
def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>; def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>; def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>; def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>; def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>; def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
//===----------------------------------------------------------------------===//
// SMEM Instructions
//===----------------------------------------------------------------------===//
def S_DCACHE_WB : SMEM_Inval <0x21,
"s_dcache_wb", int_amdgcn_s_dcache_wb>;
def S_DCACHE_WB_VOL : SMEM_Inval <0x23,
"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
def S_MEMREALTIME : SMEM_Ret<0x25,
"s_memrealtime", int_amdgcn_s_memrealtime>;
} // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI } // End SIAssemblerPredicate = DisableInst, SubtargetPredicate = isVI
let Predicates = [isVI] in { let Predicates = [isVI] in {
// 1. Offset as 20bit DWORD immediate
def : Pat <
(SIload_constant v4i32:$sbase, IMM20bit:$offset),
(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// DPP Patterns // DPP Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : Pat < def : Pat <
(int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask, (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
imm:$bound_ctrl), imm:$bound_ctrl),
(V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask), (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask),
(as_i32imm $bank_mask), (as_i1imm $bound_ctrl)) (as_i32imm $bank_mask), (as_i1imm $bound_ctrl))
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Misc Patterns // Misc Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def : Pat <
(i64 (readcyclecounter)),
(S_MEMREALTIME)
>;
} // End Predicates = [isVI] } // End Predicates = [isVI]