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[mips] MIPSR6 delay slot filler optimization.
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Authored by sdardis on Aug 4 2016, 2:50 AM.

Details

Summary

For MIPSR6 targets, stop the delay slot filler from picking an instruction
that would expose a load to CTI hazard.

Filling delay slots with 'speculative' instructions is not required. Those cases
can be turned into compact branches to avoid unnecessarily increasing codesize.

Diff Detail

Event Timeline

sdardis updated this revision to Diff 66779.Aug 4 2016, 2:50 AM
sdardis retitled this revision from to [mips] MIPSR6 delay slot filler optimization..
sdardis updated this object.
sdardis added reviewers: dsanders, vkalintiris.
sdardis set the repository for this revision to rL LLVM.
sdardis added a subscriber: llvm-commits.
vkalintiris requested changes to this revision.Oct 18 2016, 4:57 AM
vkalintiris edited edge metadata.

When I tested this I noticed that MultiSource/Benchmarks/7zip/7zip-benchmark was failing. I'm marking this with "Request Changes" to better keep track of the pending review requests.

This revision now requires changes to proceed.Oct 18 2016, 4:57 AM
dsanders resigned from this revision.Jul 18 2019, 7:03 PM
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