[mips] MIPSR6 delay slot filler optimization.

[sdardis]

Summary

For MIPSR6 targets, stop the delay slot filler from picking an instruction
that would expose a load to CTI hazard.

Filling delay slots with 'speculative' instructions is not required. Those cases
can be turned into compact branches to avoid unnecessarily increasing codesize.

[sdardis]

Ping.

[vkalintiris]

When I tested this I noticed that MultiSource/Benchmarks/7zip/7zip-benchmark was failing. I'm marking this with "Request Changes" to better keep track of the pending review requests.

lib/Target/Mips/MipsDelaySlotFiller.cpp

for (Iter I = MBB.begin(); I != MBB.end(); ++I) {
     // Delay slot filling is disabled at -O0.
     if (!DisableDelaySlotFiller && (TM.getOptLevel() != CodeGenOpt::None)) {
       bool Filled = false;
 
       if (MipsCompactBranchPolicy.getValue() != CB_Always ||
            !TII->getEquivalentCompactForm(I)) {
         if (searchBackward(MBB, I)) {
           Filled = true;
-        } else if (I->isTerminator()) {
+        // For MIPSR6, filling delay slots by searching ahead is impractical
+        // for codesize as it requires cloning the target instruction into the
+        // other paths. It can also be impractical from a performance
+        // perspective as a cloned memory access may not hit the cache.
+        } else if (!STI.hasMips32r6() || MipsCompactBranchPolicy != CB_Never){
+          if (I->isTerminator()) {
             if (searchSuccBBs(MBB, I)) {
               Filled = true;
             }
           } else if (searchForward(MBB, I)) {
             Filled = true;
           }
         }
+      }
 
       if (Filled) {
         // Get instruction with delay slot.
         MachineBasicBlock::instr_iterator DSI = I.getInstrIterator();
 
         if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 &&
             DSI->isCall()) {
           // If instruction in delay slot is 16b change opcode to
bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End,
   return false;
 }
 
 bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const {
   if (DisableBackwardSearch)
     return false;
 
   auto *Fn = MBB.getParent();
+  const MipsSubtarget &STI = Fn->getSubtarget<MipsSubtarget>();
+  const MipsInstrInfo *TII = STI.getInstrInfo();
   RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo());
   MemDefsUses MemDU(Fn->getDataLayout(), &Fn->getFrameInfo());
+  auto *TRI = Fn->getSubtarget().getRegisterInfo();
   ReverseIter Filler;
-
+  ReverseIter RI = ReverseIter(Slot);
   RegDU.init(*Slot);
 
-  if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Slot,
+  // For MIPSR6 it can be benefical to inhibit filling the delay slot of a
+  // CTI if it introduces a load->CTI hazard. Skip over the instruction
+  // covering the hazard and the load and continue the search from there.
+  if (STI.hasMips32r6() && !STI.inMicroMipsMode() &&
+      TII->getEquivalentCompactForm(Slot) && Slot != MBB.begin()) {
+
+    ReverseIter Candidate = RI;
+    bool DFTerminates = false;
+    for (; Candidate != MBB.rend() && !DFTerminates; ++Candidate) {
+      DFTerminates = terminateSearch(*Candidate);
+      if (!Candidate->isDebugValue())
+        break;
+    }
+
+    ReverseIter Load = Candidate;
+    for (Load++; Load != MBB.rend() && !DFTerminates; ++Load) {
+      DFTerminates = terminateSearch(*Load);
+      if (!Load->isDebugValue())
+        break;
+    }
+
+    if (!DFTerminates && Candidate != MBB.rend() && Load != MBB.rend() &&
+        Load->mayLoad()) {
+      BitVector BranchUses(TRI->getNumRegs());
+      BitVector LoadDefs(TRI->getNumRegs());
+      BitVector CandidateDefs(TRI->getNumRegs());
+
+      for (const MachineOperand &MO : (*Slot).uses())
+        if (MO.isReg())
+          BranchUses.set(MO.getReg());
+
+      for (const MachineOperand &MO : (*Candidate).defs())
+        if (MO.isReg())
+          CandidateDefs.set(MO.getReg());
+
+      for (const MachineOperand &MO : (*Load).defs())
+        if (MO.isReg())
+          LoadDefs.set(MO.getReg());
+
+      if (BranchUses.anyCommon(LoadDefs) &&
+          !BranchUses.anyCommon(CandidateDefs)) {
+        RI = ReverseIter(std::prev(std::prev(Slot)));
+        delayHasHazard(*std::prev(Slot), RegDU, MemDU);
+        delayHasHazard(*std::prev(std::prev(Slot)), RegDU, MemDU);
+      }
+    }
+  }
+
+  if (!searchRange(MBB, RI, MBB.rend(), RegDU, MemDU, Slot,
                    Filler))
     return false;
 
   MBB.splice(std::next(Slot), &MBB, std::next(Filler).base());
   MIBundleBuilder(MBB, Slot, std::next(Slot, 2));
   ++UsefulSlots;
   return true;
 }

test/CodeGen/Mips/compactbranches/delay-slot-filler.ll

+; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-df-forward-search=true \
+; RUN:      -disable-mips-df-succbb-search=true -disable-mips-df-backward-search \
+; RUN:       < %s | FileCheck %s -check-prefix=FORWARD
+
+; RUN: llc -march=mipsel -mcpu=mips32r6 < %s | FileCheck %s -check-prefix=BACKWARD
+
+; Test the restricted backwards delay filler. We should get the return value
+; synthesized into v0 in the delay slot of jr rather than the stack pointer
+; increment.
+declare void @k()
+
+define i32 @l9() #0 {
+; CHECK-LABEL: l9
+entry:
+  call void @k()
+
+; BACKWARD:  jr $ra
+; BACKWARD:  addiu $2, $zero, -1
+  ret i32 -1
+}
+
+; Function Attrs: norecurse nounwind
+define i32 @f(i32 signext %a, i32 signext %c, i32* nocapture %b) {
+; CHECK-LABEL: f
+entry:
+; FORWARD: beqzc
+  %tobool = icmp eq i32 %c, 0
+  br i1 %tobool, label %if.end, label %if.then
+
+if.then:                                          ; preds = %entry
+  %add = shl nsw i32 %a, 1
+  store i32 %add, i32* %b, align 4
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  %mul = mul nsw i32 %a, 6
+  ret i32 %mul
+}
+