[ELF] Implement R_ARM_TARGET1

[davide]

Summary

I hit this relocation while building some software for ARM and realized the support for that is a little bit weird. In fact, TARGET1 is interpreted as REL32 or ABS32 depending on if --target1-rel or --target1-abs is passed on the cmdline. The default behaviour seems to interpret the relocation as ABS if no option is passed.

[ruiu]

ELF/Config.h

1

Revert.

ELF/Relocations.cpp

538

This affects all targets even though only ARM needs it. It is better to add cases for TARGET1 relocation to ARMTargetInfo::getRelExpr and ARMTargetInfo::relocateOne instead.

[davide]

Makes sense. Virtual calls are expensive, alas :( I also forgot to git add the test, should be in this revision.

[ruiu]

ELF/Target.cpp

1505

I think I'd prefer adding case R_ARM_TARGET1 to the following switches because, by doing so, you don't need to read this function to understand how we handle ARM relocations for all relocation types except TARGET1. See below.

1536

case R_ARM_TARGET1:
  return Config->Target1Rel ? R_PC : R_ABS;

1558

if (Type == R_ARM_TARGET1 && !Config->Target1Rel)
  return R_ARM_ABS32;

1641

Add case R_ARM_TARGET32: so that you can remove modifyARMReloc from this function.

1770

Ditto

[davide]

Rui's comments.

[ruiu]

LGTM

ELF/Config.h

+
 //===- Config.h -------------------------------------------------*- C++ -*-===//
 //
 //                             The LLVM Linker
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
struct Configuration {
   bool Rela;
   bool Relocatable;
   bool SaveTemps;
   bool Shared;
   bool Static = false;
   bool StripAll;
   bool StripDebug;
   bool SysvHash = true;
+  bool Target1Rel;
   bool Threads;
   bool Trace;
   bool Verbose;
   bool WarnCommon;
   bool ZCombreloc;
   bool ZExecStack;
   bool ZNodelete;
   bool ZNow;

ELF/Driver.cpp

void LinkerDriver::readConfigs(opt::InputArgList &Args) {
   Config->NoUndefinedVersion = Args.hasArg(OPT_no_undefined_version);
   Config->Pie = Args.hasArg(OPT_pie);
   Config->PrintGcSections = Args.hasArg(OPT_print_gc_sections);
   Config->Relocatable = Args.hasArg(OPT_relocatable);
   Config->SaveTemps = Args.hasArg(OPT_save_temps);
   Config->Shared = Args.hasArg(OPT_shared);
   Config->StripAll = Args.hasArg(OPT_strip_all);
   Config->StripDebug = Args.hasArg(OPT_strip_debug);
+  Config->Target1Rel = Args.hasArg(OPT_target1_rel);
   Config->Threads = Args.hasArg(OPT_threads);
   Config->Trace = Args.hasArg(OPT_trace);
   Config->Verbose = Args.hasArg(OPT_verbose);
   Config->WarnCommon = Args.hasArg(OPT_warn_common);
 
   Config->DynamicLinker = getString(Args, OPT_dynamic_linker);
   Config->Entry = getString(Args, OPT_entry);
   Config->Fini = getString(Args, OPT_fini, "_fini");

ELF/Options.td

def start_lib: F<"start-lib">,
   HelpText<"Start a grouping of objects that should be treated as if they were together in an archive">;
 
 def strip_all: F<"strip-all">, HelpText<"Strip all symbols">;
 
 def strip_debug: F<"strip-debug">, HelpText<"Strip debugging information">;
 
 def sysroot: J<"sysroot=">, HelpText<"Set the system root">;
 
+def target1_rel: F<"target1-rel">, HelpText<"Interpret R_ARM_TARGET1 as R_ARM_REL32">;
+
+def target1_abs: F<"target1-abs">, HelpText<"Interpret R_ARM_TARGET1 as R_ARM_ABS32">;
+
 def threads: F<"threads">, HelpText<"Enable use of threads">;
 
 def trace: F<"trace">, HelpText<"Print the names of the input files">;
 
 def trace_symbol : J<"trace-symbol=">, HelpText<"Trace references to symbols">;
 
 def undefined: J<"undefined=">,
   HelpText<"Force undefined symbol during linking">;

ELF/Relocations.cpp

     Pieces = Eh->Pieces;
 
   ArrayRef<EhSectionPiece>::iterator PieceI = Pieces.begin();
   ArrayRef<EhSectionPiece>::iterator PieceE = Pieces.end();
 
   for (auto I = Rels.begin(), E = Rels.end(); I != E; ++I) {
     const RelTy &RI = *I;
     SymbolBody &Body = File.getRelocTargetSym(RI);
-    uint32_t Type = RI.getType(Config->Mips64EL);
+    uint32_t Type = Target->modifyReloc(RI.getType(Config->Mips64EL));
 
     RelExpr Expr = Target->getRelExpr(Type, Body);
     bool Preemptible = isPreemptible(Body, Type);
     Expr = adjustExpr(File, Body, IsWrite, Expr, Type, Buf + RI.r_offset);
     if (HasError)
       continue;
 
     // Skip a relocation that points to a dead piece

ELF/Target.h

 class SymbolBody;
 
 class TargetInfo {
 public:
   virtual bool isTlsInitialExecRel(uint32_t Type) const;
   virtual bool isTlsLocalDynamicRel(uint32_t Type) const;
   virtual bool isTlsGlobalDynamicRel(uint32_t Type) const;
   virtual uint32_t getDynRel(uint32_t Type) const { return Type; }
+  virtual uint32_t modifyReloc(uint32_t Type) const { return Type; }
   virtual void writeGotPltHeader(uint8_t *Buf) const {}
   virtual void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const {};
   virtual uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const;
 
   // If lazy binding is supported, the first entry of the PLT has code
   // to call the dynamic linker to resolve PLT entries the first time
   // they are called. This function writes that code.
   virtual void writePltHeader(uint8_t *Buf) const {}

ELF/Target.cpp

   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
 };
 
 class ARMTargetInfo final : public TargetInfo {
 public:
   ARMTargetInfo();
   RelExpr getRelExpr(uint32_t Type, const SymbolBody &S) const override;
   uint32_t getDynRel(uint32_t Type) const override;
+  uint32_t modifyReloc(uint32_t Type) const override;
   uint64_t getImplicitAddend(const uint8_t *Buf, uint32_t Type) const override;
   bool isTlsLocalDynamicRel(uint32_t Type) const override;
   bool isTlsGlobalDynamicRel(uint32_t Type) const override;
   bool isTlsInitialExecRel(uint32_t Type) const override;
   void writeGotPlt(uint8_t *Buf, const SymbolBody &S) const override;
   void writePltHeader(uint8_t *Buf) const override;
   void writePlt(uint8_t *Buf, uint64_t GotEntryAddr, uint64_t PltEntryAddr,
                 int32_t Index, unsigned RelOff) const override;

   GotEntrySize = 4;
   GotPltEntrySize = 4;
   PltEntrySize = 16;
   PltHeaderSize = 20;
   // ARM uses Variant 1 TLS
   TcbSize = 8;
   NeedsThunks = true;
 }
 
+uint32_t ARMTargetInfo::modifyReloc(uint32_t Type) const {
+  if (Type == R_ARM_TARGET1)
+    return (Config->Target1Rel) ? R_ARM_REL32 : R_ARM_ABS32;
+  return Type;
+}
+
 RelExpr ARMTargetInfo::getRelExpr(uint32_t Type, const SymbolBody &S) const {
   switch (Type) {
   default:
     return R_ABS;
   case R_ARM_THM_JUMP11:
     return R_PC;
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32:
   case R_ARM_THM_JUMP19:
   case R_ARM_THM_JUMP24:
   case R_ARM_THM_CALL:
     return R_PLT_PC;
   case R_ARM_GOTOFF32:
     // (S + A) - GOT_ORG
     return R_GOTREL;
   case R_ARM_GOT_BREL:
     // GOT(S) + A - GOT_ORG
     return R_GOT_OFF;
   case R_ARM_GOT_PREL:
   case R_ARM_TLS_IE32:
     // GOT(S) + A - P
     return R_GOT_PC;
   case R_ARM_TLS_GD32:
     return R_TLSGD_PC;
   case R_ARM_TLS_LDM32:
     return R_TLSLD_PC;
   case R_ARM_BASE_PREL:
     // B(S) + A - P
     // FIXME: currently B(S) assumed to be .got, this may not hold for all
     // platforms.
     return R_GOTONLY_PC;
   case R_ARM_MOVW_PREL_NC:
   case R_ARM_MOVT_PREL:
   case R_ARM_PREL31:
   case R_ARM_REL32:
   case R_ARM_THM_MOVW_PREL_NC:
   case R_ARM_THM_MOVT_PREL:
     return R_PC;
   case R_ARM_TLS_LE32:
     return R_TLS;
   }
 }
 
 uint32_t ARMTargetInfo::getDynRel(uint32_t Type) const {
   if (Type == R_ARM_ABS32)
     return Type;
   // Keep it going with a dummy value so that we can find more reloc errors.
   errorDynRel(Type);
   return R_ARM_ABS32;
 }
 
 void ARMTargetInfo::writeGotPlt(uint8_t *Buf, const SymbolBody &) const {
   write32le(Buf, Out<ELF32LE>::Plt->getVA());

   case R_ARM_ABS32:
   case R_ARM_BASE_PREL:
   case R_ARM_GOTOFF32:
   case R_ARM_GOT_BREL:
   case R_ARM_GOT_PREL:
   case R_ARM_REL32:
   case R_ARM_TLS_GD32:
   case R_ARM_TLS_IE32:
   case R_ARM_TLS_LDM32:
   case R_ARM_TLS_LDO32:
   case R_ARM_TLS_LE32:
     write32le(Loc, Val);
     break;
   case R_ARM_PREL31:
     checkInt<31>(Val, Type);
     write32le(Loc, (read32le(Loc) & 0x80000000) | (Val & ~0x80000000));
     break;

   case R_ARM_BASE_PREL:
   case R_ARM_GOTOFF32:
   case R_ARM_GOT_BREL:
   case R_ARM_GOT_PREL:
   case R_ARM_REL32:
   case R_ARM_TLS_GD32:
   case R_ARM_TLS_LDM32:
   case R_ARM_TLS_LDO32:
   case R_ARM_TLS_IE32:
   case R_ARM_TLS_LE32:
     return SignExtend64<32>(read32le(Buf));
   case R_ARM_PREL31:
     return SignExtend64<31>(read32le(Buf));
   case R_ARM_CALL:
   case R_ARM_JUMP24:
   case R_ARM_PC24:
   case R_ARM_PLT32: