AMDGPU Device Libs pass.

[nhaustov]

Summary

Replace calls to __oclc_option_mask in a kernel.

If there is call to __oclc_option_mask in a function,
add option mask as argument and pass it through all calls to this function.

[• tstellarAMD]

lib/Target/AMDGPU/AMDGPUDeviceLibs.h

2

Header comment is missing.

6

Can you add a comment explaining what this option is for.

lib/Target/AMDGPU/AMDGPUDeviceLibsPass.cpp

2

This file needs a header comment with an explanation of what it does.

39

Do we want to set this even at -O0 ?

58

Coding style: brace shouldn't be on its own line.

77

Coding Style.

91

Coding Style.

138

Coding Style.

[arsenm]

Should this really be in the backend? I also thought we were going to use a global constant variable instead of a function call

[nhaustov]

In D22751#494940, @arsenm wrote:

Should this really be in the backend? I also thought we were going to use a global constant variable instead of a function call

Yes, it needs to be. Global variable approach doesn't support functions in different modes.
Any specific concerns with the patch?

[arsenm]

In D22751#494978, @nhaustov wrote:

In D22751#494940, @arsenm wrote:

Should this really be in the backend? I also thought we were going to use a global constant variable instead of a function call

Yes, it needs to be. Global variable approach doesn't support functions in different modes.
Any specific concerns with the patch?

The idea was that would be controlled by multiple globals with private visibility in different modules linked together.
Why does it need to be in the backend? This seems more like a pass that belongs with the runtime/compiler library when linking the AMD specific library

[nhaustov]

In D22751#494984, @arsenm wrote:

In D22751#494978, @nhaustov wrote:

In D22751#494940, @arsenm wrote:

Should this really be in the backend? I also thought we were going to use a global constant variable instead of a function call

Yes, it needs to be. Global variable approach doesn't support functions in different modes.
Any specific concerns with the patch?

The idea was that would be controlled by multiple globals with private visibility in different modules linked together.
Why does it need to be in the backend? This seems more like a pass that belongs with the runtime/compiler library when linking the AMD specific library

Multiple variables would not work with function calls (see example with call in the review).

Yes, it will be run before backend passes (in pre-link phase). It's common for all languages though.

[nhaustov]

Update after Tom's review.

[nhaustov]

lib/Target/AMDGPU/AMDGPUDeviceLibsPass.cpp

40

Since the linking is at bitcode level, we can. We should review it later.

[yaxunl]

Can we have a test like this:

int f() {
  if (__oclc_option_mask() & X)
    return 1
  else if (__oclc_option_mask() & Y)
    return 2;
}

then call it in different kernels.

test/CodeGen/AMDGPU/device-libs.ll

45

Can we have another kernel calling get_option_mask2() with different function attributes?

[arsenm]

lib/Target/AMDGPU/AMDGPUDeviceLibsPass.cpp

60–65

if bodies on separate lines

143–147

Why do we have to handle this GC bit? needs tests

164–181

Should make common with CallSite. Why does invoke need to be handled at all? No library function should ever throw

205–206

pop_back_val?

[nhaustov]

• Update after Matt's review.

lib/Target/AMDGPU/AMDGPUDeviceLibsPass.cpp

60–65

Rewrote.

143–147

Removed.

164–181

What do you mean 'common with CallSite'?
I've removed invoke.

205–206

It's std::set which doesn't have it.

[yaxunl]

I am thinking probably this should be a post-linking pass.

The library functions can be identified by prefixes or name mangling. All OpenCL builtin functions start with _Z ( IA64 mangled ) and other library functions have specific prefixes. We add an extra option argument to all library functions. If a library function calls other library functions, pass this option argument down.

Non-library functions are compiled with cl- options which become function attributes. We just need to translate them to option mask and pass it to the OpenCL buitin functions called by this non-library function.

After this transformation, all library function calls will have an option argument equivalent to the cl- options they are compiled with in the original compilation unit.

[nhaustov]

Due to difficulties, it was decided to pursue different approach - create control functions in Runtime and link them as bitcode libraries.

lib/Target/AMDGPU/AMDGPU.h

 
 FunctionPass *createAMDGPUAddDivergenceMetadata(const AMDGPUSubtarget &ST);
 Pass *createAMDGPUStructurizeCFGPass();
 FunctionPass *createAMDGPUISelDag(TargetMachine &tm);
 ModulePass *createAMDGPUAlwaysInlinePass();
 ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
 FunctionPass *createAMDGPUAnnotateUniformValues();
 
+void initializeAMDGPUDeviceLibsPass(PassRegistry &);
+ModulePass *createAMDGPUDeviceLibsPass(TargetMachine& tm);
+
 void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
 extern char &SIFixControlFlowLiveIntervalsID;
 
 void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
 extern char &AMDGPUAnnotateUniformValuesPassID;
 
 void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
 extern char &AMDGPUCodeGenPrepareID;

lib/Target/AMDGPU/AMDGPUDeviceLibs.h

+//===-- AMDGPUDeviceLibs.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+/// \file
+///
+/// Definitions used by device libraries.
+///
+//===----------------------------------------------------------------------===//
+#ifndef AMDGPU_DEVICE_LIBS_H
+#define AMDGPU_DEVICE_LIBS_H
+
+//
+// Components of option mask, 64-bit value that determines library code.
+//
+enum AMDGPUOptionMask {
+  // Enable AMD hardware optimization. Always set for AMDGPU backend.
+  AMD_OPT = 1,
+
+  // Enable unsafe math optimizations.
+  UNSAFE_FP_MATH = 2,
+
+  // No NaNs.
+  NO_NANS_FP_MATH = 4,
+
+  // No INFs.
+  NO_INFS_FP_MATH = 8,
+
+  // Device supports fast FMA32.
+  FAST_FMA32 = 16,
+
+  // Device supports fast FMA64.
+  FAST_FMA64 = 32,
+
+  // FP32 denorms are enabled.
+  FP32_DENORMS = 64,
+
+  // FP64 denorms are enabled.
+  FP64_DENORMS = 128,
+
+  // Position of first bit of ISA version.
+  ISA_VERSION_SHIFT = 8,
+
+  // Width of ISA version.
+  ISA_VERSION_WIDTH = 4,
+};
+
+#endif /* AMDGPU_DEVICE_LIBS_H */

lib/Target/AMDGPU/AMDGPUDeviceLibsPass.cpp

+//===-- AMDGPUDeviceLibsPass.cpp - device libraries related IR processing --===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+///
+/// AMDGPUDeviceLibsPass implements additional processing for device libraries.
+///
+/// Replace calls to __oclc_option_mask in a kernel with option mask value.
+///
+/// If non-kernel function uses option mask, pass it as additoinal argument.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AMDGPU.h"
+#include "llvm/IR/Constants.h"
+#include "llvm/IR/Function.h"
+#include "llvm/IR/InstIterator.h"
+#include "llvm/IR/GlobalVariable.h"
+#include "llvm/IR/Verifier.h"
+#include "llvm/CodeGen/Passes.h"
+#include "AMDGPUSubtarget.h"
+#include "AMDGPUDeviceLibs.h"
+
+#define DEBUG_TYPE "amdgpu-device-libs"
+
+using namespace llvm;
+
+namespace {
+
+class AMDGPUDeviceLibs : public ModulePass {
+  const TargetMachine* TM;
+
+  uint64_t KernelOptionMask(Function& F);
+
+  bool IsAttributeSet(Function &F, StringRef Attr) {
+    return
+      F.hasFnAttribute(Attr) &&
+      (F.getFnAttribute(Attr).getValueAsString() != "false");
+  }
+
+  void SetBits(uint64_t& mask, uint64_t bits, bool set = true) {
+    if (set) {
+      mask |= bits;
+    }
+  }
+
+public:
+  static char ID;
+  AMDGPUDeviceLibs(const TargetMachine* TM_ = 0)
+    : ModulePass(ID), TM(TM_) {}
+
+  bool runOnModule(Module &M) override;
+};
+
+uint64_t AMDGPUDeviceLibs::KernelOptionMask(Function& F) {
+  uint64_t mask = 0;
+  SetBits(mask, AMD_OPT); // Always set.
+  SetBits(mask, UNSAFE_FP_MATH, IsAttributeSet(F, "unsafe-fp-math"));
+  SetBits(mask, NO_NANS_FP_MATH, IsAttributeSet(F, "no-nans-fp-math"));
+  SetBits(mask, NO_INFS_FP_MATH, IsAttributeSet(F, "no-infs-fp-math"));
+  const SISubtarget* ST = static_cast<const SISubtarget*>(TM->getSubtargetImpl(F));
+  SetBits(mask, FAST_FMA32, ST->hasFastFMAF32());
+  AMDGPU::IsaVersion ISA = ST->getIsaVersion();
+  SetBits(mask, (ISA.Major * 100 + ISA.Minor * 10 + ISA.Stepping) << ISA_VERSION_SHIFT);
+  return mask;
+}
+
+struct NewArgInfo {
+  Type *Ty;
+  const char *Name;
+};
+
+FunctionType *GetFunctionTypeWithNewArguments(FunctionType *FTy,
+                                              ArrayRef<NewArgInfo> NArgs) {
+  unsigned NumNArgs = NArgs.size();
+  SmallVector<Type *, 16> ArgTypes;
+  ArgTypes.reserve(NumNArgs + FTy->getNumParams());
+
+  unsigned Idx;
+  for (Idx = 0; Idx != NumNArgs; ++Idx)
+    ArgTypes.push_back(NArgs[Idx].Ty);
+
+  ArgTypes.insert(ArgTypes.end(), FTy->param_begin(), FTy->param_end());
+
+
+  return FunctionType::get(FTy->getReturnType(), ArgTypes, FTy->isVarArg());
+}
+
+static AttributeSet ShiftAttributes(LLVMContext &Ctx,
+                                    const AttributeSet& PAL,
+                                    unsigned NumParams,
+                                    unsigned Shift) {
+  SmallVector<AttributeSet, 8> Attributes;
+  Attributes.push_back(AttributeSet::get(Ctx, PAL.getRetAttributes()));
+  for (unsigned Idx = 1; Idx <= NumParams; ++Idx) {
+    AttributeSet params = PAL.getParamAttributes(Idx);
+    AttrBuilder B(params, Idx);
+    Attributes.push_back(AttributeSet::get(Ctx, Idx + Shift, B));
+  }
+  Attributes.push_back(AttributeSet::get(Ctx, PAL.getFnAttributes()));
+  return AttributeSet::get(Ctx, Attributes);
+}
+
+Function *CreateFunctionWithNewArguments(Function* F,
+                                         ArrayRef<NewArgInfo> NArgs) {
+  unsigned NumNArgs = NArgs.size();
+
+  // Create a new function type
+  FunctionType *NFTy = cast<FunctionType>(F->getType()->getElementType());
+  NFTy = GetFunctionTypeWithNewArguments(NFTy, NArgs);
+
+  // Create the new function
+  Function *NF = Function::Create(NFTy, F->getLinkage());
+  F->getParent()->getFunctionList().insert(F->getIterator(), NF);
+
+  Function::arg_iterator NI = NF->arg_begin();
+  for (unsigned Idx = 0; Idx != NumNArgs; ++Idx, ++NI)
+    if (const char *NName = NArgs[Idx].Name)
+      NI->setName(NName);
+
+  // Since we have now created the new function, splice the body of the old
+  // function right into the new function, leaving the old rotting hulk of the
+  // function empty.
+  NF->takeName(F);
+  NF->getBasicBlockList().splice(NF->begin(), F->getBasicBlockList());
+
+  // Loop over the argument list, transferring uses of the old arguments over
+  // to the new arguments, also transferring over the names as well.
+  for (Function::arg_iterator I = F->arg_begin(), E = F->arg_end();
+       I != E; ++I, ++NI) {
+    I->replaceAllUsesWith(&*NI);
+    NI->takeName(&*I);
+  }
+
+  NF->GlobalValue::copyAttributesFrom(F);
+  NF->setAttributes(ShiftAttributes(F->getParent()->getContext(),
+                                    F->getAttributes(),
+                                    (unsigned)F->arg_size(),
+                                    NumNArgs));
+
+  NF->setCallingConv(F->getCallingConv());
+
+  return NF;
+}
+
+void AddArgumentsToCallSite(CallSite &CS, SmallVectorImpl<Value*> &Args,
+                            Value *Callee) {
+  Instruction *Call = CS.getInstruction();
+  unsigned NumNArgs = (unsigned)Args.size();
+
+  Args.insert(Args.end(), CS.arg_begin(), CS.arg_end());
+
+  auto NPAL = ShiftAttributes(CS.getCaller()->getParent()->getContext(),
+                              CS.getAttributes(),
+                              (unsigned)CS.arg_size(), NumNArgs);
+
+  CallInst *CI = cast<CallInst>(Call);
+  CallInst *NCI = CallInst::Create(Callee, Args, "", Call);
+  NCI->setCallingConv(CI->getCallingConv());
+  NCI->setAttributes(NPAL);
+  if (CI->isTailCall())
+    NCI->setTailCall();
+
+  Instruction *NCall = NCI;
+  NCall->setDebugLoc(Call->getDebugLoc());
+
+  if (!Call->use_empty())
+    Call->replaceAllUsesWith(NCall);
+
+  NCall->takeName(Call);
+
+  // Remove the old call from the program, reducing the use-count of F.
+  Call->eraseFromParent();
+}
+
+bool AMDGPUDeviceLibs::runOnModule(Module &M) {
+  bool Changed = false;
+  SmallVector<Instruction *, 16> ToRemove;
+
+  std::set<Function*> Worklist, Functions;
+  std::set<CallInst*> Calls;
+
+  for (Function& F : M.getFunctionList()) {
+    Worklist.insert(&F);
+  }
+
+  while (!Worklist.empty()) {
+    Function* F = *Worklist.begin();
+    Worklist.erase(F);
+    Changed = false;
+    for (Instruction &I : instructions(F)) {
+      CallInst *Call = dyn_cast<CallInst>(&I);
+      if (!Call)
+        continue;
+      Function *Callee = Call->getCalledFunction();
+      if (!Callee)
+        continue;
+      if (Callee->getName() == "__oclc_option_mask" ||
+          Functions.find(Callee) != Functions.end()) {
+        Changed |= Functions.insert(F).second;
+        Changed |= Calls.insert(Call).second;
+      }
+    }
+    if (Changed) {
+      for (Use& US : F->uses()) {
+        User* U = US.getUser();
+        if (Instruction *Inst = dyn_cast<Instruction>(U)) {
+          Function* Caller = Inst->getFunction();
+          if (Functions.find(Caller) == Functions.end()) {
+            Functions.insert(Caller);
+            Worklist.insert(Caller);
+          }
+        }
+      }
+    }
+  }
+
+  std::map<Function*, Function*> NewFunctions;
+
+  for (Function* F : Functions) {
+    if (F->getCallingConv() == llvm::CallingConv::AMDGPU_KERNEL ||
+        F->getCallingConv() == llvm::CallingConv::SPIR_KERNEL) {
+      continue;
+    }
+    SmallVector<NewArgInfo, 1> NewArgsInfo;
+    NewArgInfo Info;
+    Info.Ty = IntegerType::get(M.getContext(), 64);
+    Info.Name = "__option_mask";
+    NewArgsInfo.push_back(Info);
+    Function* NF = CreateFunctionWithNewArguments(F, NewArgsInfo);
+    NewFunctions[F] = NF;
+  }
+
+  for (CallInst* Call : Calls) {
+    Function* Caller = Call->getFunction();
+    Function* Callee = Call->getCalledFunction();
+    Value* OptionMask = nullptr;
+    if (Caller->getCallingConv() == llvm::CallingConv::AMDGPU_KERNEL ||
+        Caller->getCallingConv() == llvm::CallingConv::SPIR_KERNEL) {
+      OptionMask = ConstantInt::get(Call->getType(), KernelOptionMask(*Caller));
+    } else {
+      for (Argument& arg : Caller->args()) {
+        if (arg.getName() == "__option_mask") {
+          OptionMask = &arg;
+          break;
+        }
+      }
+    }
+    assert(OptionMask);
+
+    if (Callee->getName() == "__oclc_option_mask") {
+      Call->replaceAllUsesWith(OptionMask);
+      ToRemove.push_back(Call);
+    } else {
+      CallSite CS(Call);
+      Function* NewCallee = NewFunctions[Callee];
+      Call->replaceUsesOfWith(Callee, NewCallee);
+      SmallVector<Value*, 16> NewArgs;
+      NewArgs.push_back(OptionMask);
+      AddArgumentsToCallSite(CS, NewArgs, NewCallee);
+    }
+  }
+
+  for (Instruction *I : ToRemove)
+    I->eraseFromParent();
+  return ToRemove.size() > 0;
+}
+
+char AMDGPUDeviceLibs::ID = 0;
+}
+
+ModulePass *llvm::createAMDGPUDeviceLibsPass(TargetMachine& tm) {
+  return new AMDGPUDeviceLibs(&tm);
+}
+
+INITIALIZE_TM_PASS(AMDGPUDeviceLibs, DEBUG_TYPE,
+                   "AMDGPU Device libraries pass", false, false)

lib/Target/AMDGPU/AMDGPUTargetMachine.h

public:
   const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
     return &IntrinsicInfo;
   }
   TargetIRAnalysis getTargetIRAnalysis() override;
 
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
+  void addPreLinkPasses(PassManagerBase &) override;
 };
 
 //===----------------------------------------------------------------------===//
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
 class R600TargetMachine final : public AMDGPUTargetMachine {
 private:

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

extern "C" void LLVMInitializeAMDGPUTarget() {
   initializeAMDGPUPromoteAllocaPass(*PR);
   initializeAMDGPUCodeGenPreparePass(*PR);
   initializeSIAnnotateControlFlowPass(*PR);
   initializeSIDebuggerInsertNopsPass(*PR);
   initializeSIInsertWaitsPass(*PR);
   initializeSIWholeQuadModePass(*PR);
   initializeSILowerControlFlowPass(*PR);
   initializeSIDebuggerInsertNopsPass(*PR);
+  initializeAMDGPUDeviceLibsPass(*PR);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   return make_unique<AMDGPUTargetObjectFile>();
 }
 
 static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
   return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());

 StringRef AMDGPUTargetMachine::getFeatureString(const Function &F) const {
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   return FSAttr.hasAttribute(Attribute::None) ?
     getTargetFeatureString() :
     FSAttr.getValueAsString();
 }
 
+void AMDGPUTargetMachine::addPreLinkPasses(PassManagerBase &PM) {
+  PM.add(createAMDGPUDeviceLibsPass(*this));
+}
+
 //===----------------------------------------------------------------------===//
 // R600 Target Machine (R600 -> Cayman)
 //===----------------------------------------------------------------------===//
 
 R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
                                      StringRef CPU, StringRef FS,
                                      TargetOptions Options,
                                      Optional<Reloc::Model> RM,

lib/Target/AMDGPU/CMakeLists.txt

 
 add_llvm_target(AMDGPUCodeGen
   AMDILCFGStructurizer.cpp
   AMDGPUAlwaysInlinePass.cpp
   AMDGPUAnnotateKernelFeatures.cpp
   AMDGPUAnnotateUniformValues.cpp
   AMDGPUAsmPrinter.cpp
   AMDGPUCodeGenPrepare.cpp
+  AMDGPUDeviceLibsPass.cpp
   AMDGPUFrameLowering.cpp
   AMDGPUTargetObjectFile.cpp
   AMDGPUIntrinsicInfo.cpp
   AMDGPUISelDAGToDAG.cpp
   AMDGPUMCInstLower.cpp
   AMDGPUMachineFunction.cpp
   AMDGPUOpenCLImageTypeLoweringPass.cpp
   AMDGPUSubtarget.cpp

test/CodeGen/AMDGPU/device-libs.ll

+; RUN: opt -S -verify-machineinstrs -amdgpu-device-libs -inline -mtriple=amdgcn-unknown-amdhsa -mcpu=hawaii < %s | FileCheck --check-prefix=SI %s
+; RUN: opt -S -verify-machineinstrs -amdgpu-device-libs -inline -mtriple=amdgcn-unknown-amdhsa -mcpu=fiji < %s | FileCheck --check-prefix=VI %s
+
+declare extern_weak i64 @__oclc_option_mask() local_unnamed_addr
+
+define i64 @get_option_mask() local_unnamed_addr #0 {
+entry:
+  %call = tail call i64 @__oclc_option_mask() #1
+  ret i64 %call
+}
+
+define i64 @get_option_mask2() local_unnamed_addr #0 {
+entry:
+  %call = tail call i64 @get_option_mask() #1
+  ret i64 %call
+}
+
+
+; FUNC-LABEL: {{^}}default_kernel:
+; SI: store i64 179473, i64 addrspace(1)* %out
+; VI: store i64 205569, i64 addrspace(1)* %out
+define amdgpu_kernel void @default_kernel(i64 addrspace(1)* nocapture %out) local_unnamed_addr #2 {
+entry:
+  %call = tail call i64 @__oclc_option_mask() #1
+  store i64 %call, i64 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}default_call_kernel:
+; SI: store i64 179473, i64 addrspace(1)* %out
+; VI: store i64 205569, i64 addrspace(1)* %out
+define amdgpu_kernel void @default_call_kernel(i64 addrspace(1)* nocapture %out) local_unnamed_addr #2 {
+entry:
+  %call = tail call i64 @get_option_mask() #0
+  store i64 %call, i64 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}default_call2_kernel:
+; SI: store i64 179473, i64 addrspace(1)* %out
+; VI: store i64 205569, i64 addrspace(1)* %out
+define amdgpu_kernel void @default_call2_kernel(i64 addrspace(1)* nocapture %out) local_unnamed_addr #2 {
+entry:
+  %call = tail call i64 @get_option_mask2() #0
+  store i64 %call, i64 addrspace(1)* %out, align 4
+  ret void
+}
+
+
+; FUNC-LABEL: {{^}}unsafe_fp_kernel:
+; SI: store i64 179475, i64 addrspace(1)* %out
+; VI: store i64 205571, i64 addrspace(1)* %out
+define amdgpu_kernel void @unsafe_fp_kernel(i64 addrspace(1)* nocapture %out) local_unnamed_addr #3 {
+entry:
+  %call = tail call i64 @__oclc_option_mask() #1
+  store i64 %call, i64 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}no_nans_fp_math_kernel:
+; SI: store i64 179477, i64 addrspace(1)* %out
+; VI: store i64 205573, i64 addrspace(1)* %out
+define amdgpu_kernel void @no_nans_fp_math_kernel(i64 addrspace(1)* nocapture %out) local_unnamed_addr #4 {
+entry:
+  %call = tail call i64 @__oclc_option_mask() #1
+  store i64 %call, i64 addrspace(1)* %out, align 4
+  ret void
+}
+
+; FUNC-LABEL: {{^}}no_infs_fp_math_kernel:
+; SI: store i64 179481, i64 addrspace(1)* %out
+; VI: store i64 205577, i64 addrspace(1)* %out
+define amdgpu_kernel void @no_infs_fp_math_kernel(i64 addrspace(1)* nocapture %out) local_unnamed_addr #5 {
+entry:
+  %call = tail call i64 @__oclc_option_mask() #1
+  store i64 %call, i64 addrspace(1)* %out, align 4
+  ret void
+}
+
+attributes #0 = { nounwind }
+attributes #1 = { nounwind readnone }
+attributes #2 = { nounwind }
+attributes #3 = { nounwind "unsafe-fp-math"="true" }
+attributes #4 = { nounwind "no-nans-fp-math"="true" }
+attributes #5 = { nounwind "no-infs-fp-math"="true" }