MachineFunction: Introduce NoPHIs property

[MatzeB]

Summary

I want to compute the SSA property of .mir files automatically in
an upcoming patch. The problem with this is that some inputs will be
reported as static single assignment and some passes subsequently reject them.
In reality though those passes have no problem with register only being assigned once but they do not support PHI
instructions.
So we track the presence of PHI instructions separate from the SSA property.

[arsenm]

lib/CodeGen/MachineFunction.cpp

77

This seems more convoluted than
if (HasProperty)

ROS << ...

[qcolombet]

lib/CodeGen/RegAllocBase.cpp

65 ↗

(On Diff #65210)

Use the getRequiredProperties method that are built in the machine function passes instead of an assert.

lib/CodeGen/RegAllocFast.cpp

1100–1101

Ditto.

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

434

Ditto.

[MatzeB]

Address review comments.

[qcolombet]

LGTM, with one nitpick.

lib/CodeGen/MIRParser/MIRParser.cpp

290

return instead and get rid of the NoPHIs variable.

include/llvm/CodeGen/MachineFunction.h

 
 public:
   // The properties are stated in "positive" form; i.e. a pass could require
   // that the property hold, but not that it does not hold.
 
   // Property descriptions:
   // IsSSA: True when the machine function is in SSA form and virtual registers
   //  have a single def.
+  // NoPHIs: The machine function does not contain any PHI instruction.
   // TracksLiveness: True when tracking register liveness accurately.
   //  While this property is set, register liveness information in basic block
   //  live-in lists and machine instruction operands (e.g. kill flags, implicit
   //  defs) is accurate. This means it can be used to change the code in ways
   //  that affect the values in registers, for example by the register
   //  scavenger.
   //  When this property is clear, liveness is no longer reliable.
   // AllVRegsAllocated: All virtual registers have been allocated; i.e. all
public:
   //  generic instructions have been eliminated; i.e., all instructions are now
   //  target-specific or non-pre-isel generic instructions (e.g., COPY).
   //  Since only pre-isel generic instructions can have generic virtual register
   //  operands, this also means that all generic virtual registers have been
   //  constrained to virtual registers (assigned to register classes) and that
   //  all sizes attached to them have been eliminated.
   enum class Property : unsigned {
     IsSSA,
+    NoPHIs,
     TracksLiveness,
     AllVRegsAllocated,
     Legalized,
     RegBankSelected,
     Selected,
     LastProperty = Selected,
   };
 

lib/CodeGen/MIRParser/MIRParser.cpp

private:
   /// Return null if the name isn't a register class.
   const TargetRegisterClass *getRegClass(const MachineFunction &MF,
                                          StringRef Name);
 
   /// Check if the given identifier is a name of a register bank.
   ///
   /// Return null if the name isn't a register bank.
   const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);
+
+  void computeFunctionProperties(MachineFunction &MF);
 };
 
 } // end namespace llvm
 
 MIRParserImpl::MIRParserImpl(std::unique_ptr<MemoryBuffer> Contents,
                              StringRef Filename, LLVMContext &Context)
     : SM(), Filename(Filename), Context(Context) {
   SM.AddNewSourceBuffer(std::move(Contents), SMLoc());

 void MIRParserImpl::createDummyFunction(StringRef Name, Module &M) {
   auto &Context = M.getContext();
   Function *F = cast<Function>(M.getOrInsertFunction(
       Name, FunctionType::get(Type::getVoidTy(Context), false)));
   BasicBlock *BB = BasicBlock::Create(Context, "entry", F);
   new UnreachableInst(Context, BB);
 }
 
+void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
+  bool NoPHIs = true;
+  for (const MachineBasicBlock &MBB : MF) {
+    for (const MachineInstr &MI : MBB) {
+      if (MI.isPHI()) {
+        NoPHIs = false;
+        break;
+      }
+    }
+  }
+  if (NoPHIs)
+    MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+}
+
 bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   auto It = Functions.find(MF.getName());
   if (It == Functions.end())
     return error(Twine("no machine function information for function '") +
                  MF.getName() + "' in the MIR file");
   // TODO: Recreate the machine function.
   const yaml::MachineFunction &YamlMF = *It->getValue();
   if (YamlMF.Alignment)
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   if (parseMachineInstructions(PFS, InsnStr, Error)) {
     reportDiagnostic(
         diagFromBlockStringDiag(Error, YamlMF.Body.Value.SourceRange));
     return true;
   }
   PFS.SM = &SM;
 
   inferRegisterInfo(PFS, YamlMF);
+
+  computeFunctionProperties(MF);
+
   // FIXME: This is a temporary workaround until the reserved registers can be
   // serialized.
   MF.getRegInfo().freezeReservedRegs(MF);
   MF.verify();
   return false;
 }
 
 bool MIRParserImpl::initializeRegisterInfo(PerFunctionMIParsingState &PFS,

lib/CodeGen/MachineFunction.cpp

 void MachineFunctionInitializer::anchor() {}
 
 static const char *getPropertyName(MachineFunctionProperties::Property Prop) {
   typedef MachineFunctionProperties::Property P;
   switch(Prop) {
   case P::AllVRegsAllocated: return "AllVRegsAllocated";
   case P::IsSSA: return "IsSSA";
   case P::Legalized: return "Legalized";
+  case P::NoPHIs: return "NoPHIs";
   case P::RegBankSelected: return "RegBankSelected";
   case P::Selected: return "Selected";
   case P::TracksLiveness: return "TracksLiveness";
   }
   llvm_unreachable("Invalid machine function property");
 }
 
 void MachineFunctionProperties::print(raw_ostream &OS) const {
   const char *Separator = "";
   for (BitVector::size_type I = 0; I < Properties.size(); ++I) {
     if (!Properties[I])
       continue;
     OS << Separator << getPropertyName(static_cast<Property>(I));
     Separator = ", ";
   }
 }
 
 //===----------------------------------------------------------------------===//
 // MachineFunction implementation
 //===----------------------------------------------------------------------===//
 
 // Out-of-line virtual method.

lib/CodeGen/MachineVerifier.cpp

 void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
   const MCInstrDesc &MCID = MI->getDesc();
   if (MI->getNumOperands() < MCID.getNumOperands()) {
     report("Too few operands", MI);
     errs() << MCID.getNumOperands() << " operands expected, but "
         << MI->getNumOperands() << " given.\n";
   }
 
+  if (MI->isPHI() && MF->getProperties().hasProperty(
+          MachineFunctionProperties::Property::NoPHIs))
+    report("Found PHI instruction with NoPHIs property set", MI);
+
   // Check the tied operands.
   if (MI->isInlineAsm())
     verifyInlineAsm(MI);
 
   // Check the MachineMemOperands for basic consistency.
   for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
        E = MI->memoperands_end(); I != E; ++I) {
     if ((*I)->isLoad() && !MI->mayLoad())

lib/CodeGen/PHIElimination.cpp

if (LIS)
       LIS->RemoveMachineInstrFromMaps(*I.first);
     MF.DeleteMachineInstr(I.first);
   }
 
   LoweredPHIs.clear();
   ImpDefs.clear();
   VRegPHIUseCount.clear();
 
+  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+
   return Changed;
 }
 
 /// EliminatePHINodes - Eliminate phi nodes by inserting copy instructions in
 /// predecessor basic blocks.
 ///
 bool PHIElimination::EliminatePHINodes(MachineFunction &MF,
                                              MachineBasicBlock &MBB) {

lib/CodeGen/RegAllocBasic.cpp

public:
   }
 
   unsigned selectOrSplit(LiveInterval &VirtReg,
                          SmallVectorImpl<unsigned> &SplitVRegs) override;
 
   /// Perform register allocation.
   bool runOnMachineFunction(MachineFunction &mf) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::NoPHIs);
+  }
+
   // Helper for spilling all live virtual registers currently unified under preg
   // that interfere with the most recently queried lvr.  Return true if spilling
   // was successful, and append any new spilled/split intervals to splitLVRs.
   bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
                           SmallVectorImpl<unsigned> &SplitVRegs);
 
   static char ID;
 };

lib/CodeGen/RegAllocFast.cpp

const char *getPassName() const override {
       return "Fast Register Allocator";
     }
 
     void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       MachineFunctionPass::getAnalysisUsage(AU);
     }
 
+    MachineFunctionProperties getRequiredProperties() const override {
+      return MachineFunctionProperties().set(
+          MachineFunctionProperties::Property::NoPHIs);
+    }
+
     MachineFunctionProperties getSetProperties() const override {
       return MachineFunctionProperties().set(
           MachineFunctionProperties::Property::AllVRegsAllocated);
     }
 
   private:
     bool runOnMachineFunction(MachineFunction &Fn) override;
     void AllocateBasicBlock();
bool RAFast::runOnMachineFunction(MachineFunction &Fn) {
   MF = &Fn;
   MRI = &MF->getRegInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
   TII = MF->getSubtarget().getInstrInfo();
   MRI->freezeReservedRegs(Fn);
   RegClassInfo.runOnMachineFunction(Fn);
   UsedInInstr.clear();
   UsedInInstr.setUniverse(TRI->getNumRegUnits());
 
-  assert(!MRI->isSSA() && "regalloc requires leaving SSA");
-
   // initialize the virtual->physical register map to have a 'null'
   // mapping for all virtual registers
   StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
   LiveVirtRegs.setUniverse(MRI->getNumVirtRegs());
 
   // Loop over all of the basic blocks, eliminating virtual register references
   for (MachineFunction::iterator MBBi = Fn.begin(), MBBe = Fn.end();
        MBBi != MBBe; ++MBBi) {
     MBB = &*MBBi;

lib/CodeGen/RegAllocGreedy.cpp

public:
   void enqueue(LiveInterval *LI) override;
   LiveInterval *dequeue() override;
   unsigned selectOrSplit(LiveInterval&, SmallVectorImpl<unsigned>&) override;
   void aboutToRemoveInterval(LiveInterval &) override;
 
   /// Perform register allocation.
   bool runOnMachineFunction(MachineFunction &mf) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::NoPHIs);
+  }
+
   static char ID;
 
 private:
   unsigned selectOrSplitImpl(LiveInterval &, SmallVectorImpl<unsigned> &,
                              SmallVirtRegSet &, unsigned = 0);
 
   bool LRE_CanEraseVirtReg(unsigned) override;
   void LRE_WillShrinkVirtReg(unsigned) override;

lib/CodeGen/RegAllocPBQP.cpp

public:
   }
 
   /// PBQP analysis usage.
   void getAnalysisUsage(AnalysisUsage &au) const override;
 
   /// Perform register allocation
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+        MachineFunctionProperties::Property::NoPHIs);
+  }
+
 private:
 
   typedef std::map<const LiveInterval*, unsigned> LI2NodeMap;
   typedef std::vector<const LiveInterval*> Node2LIMap;
   typedef std::vector<unsigned> AllowedSet;
   typedef std::vector<AllowedSet> AllowedSetMap;
   typedef std::pair<unsigned, unsigned> RegPair;
   typedef std::map<RegPair, PBQP::PBQPNum> CoalesceMap;

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

public:
   bool optimizeBlock(MachineBasicBlock &MBB);
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "SI Load / Store Optimizer";
   }
 
+  MachineFunctionProperties getRequiredProperties() const override {
+    return MachineFunctionProperties().set(
+      MachineFunctionProperties::Property::AllVRegsAllocated);
+  }
+
   void getAnalysisUsage(AnalysisUsage &AU) const override {
     AU.setPreservesCFG();
     AU.addPreserved<SlotIndexes>();
     AU.addPreserved<LiveIntervals>();
     AU.addPreserved<LiveVariables>();
     AU.addRequired<LiveIntervals>();
 
     MachineFunctionPass::getAnalysisUsage(AU);
bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
   TRI = &TII->getRegisterInfo();
 
   MRI = &MF.getRegInfo();
 
   LIS = &getAnalysis<LiveIntervals>();
 
   DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
 
-  assert(!MRI->isSSA());
-
   bool Modified = false;
 
   for (MachineBasicBlock &MBB : MF)
     Modified |= optimizeBlock(MBB);
 
   return Modified;
 }