Wrong code generation for VSX floating-point loads with fast-isel

[uweigand]

Summary

See https://llvm.org/bugs/show_bug.cgi?id=28630 for a description of the problem.

There were two locations where fast-isel would generate a LFD instruction with a target register class VSFRC instead of F8RC when VSX was enabled. The first is PPCFastISel::PPCEmitLoad, which had multiple problems:

1.) Typo in the definition of is64VSXLoad:

bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD;

The second line needs to use isVSFRC (like PPCEmitStore does)

2.) Move creation of resultReg. Even if the above typo is fixed, IsVSFRC would often be wrong, because it is computed from resultReg -- but in many cases, resultReg was still zero at this point.

3.) Once both the above are fixed, we're now generating a VSX instruction -- but an incorrect one, since generation of an indexed instruction with null index is wrong. Fixed by copying the code handling the same issue in PPCEmitStore.

The second place is PPCFastISel::PPCMaterializeFP, where we would emit an LFD to load a constant from the literal pool, and use the wrong result register class. Fixed by hardcoding a F8RC class even on systems supporting VSX.

[amehsan]

I have confirmed that this patch will also fix PR27718

[kbarton]

lib/Target/PowerPC/PPCFastISel.cpp

528

Should these two utility routines now change?
In particular, don't need to check for ResultReg != 0, since that should never happen. They can also get the register class ID from the UseRC variable directly, instead of having to look it up through the MRI (lines 149, 152).

[uweigand]

lib/Target/PowerPC/PPCFastISel.cpp

528–529

OK, I've changed the helper routines to take a regclass instead of a register. This means we don't even need to move the initialization of ResultReg, since UseRC is already set up correctly in either case here.

[kbarton]

LGTM

lib/Target/PowerPC/PPCFastISel.cpp

case MVT::f64:
       break;
   }
 
   // If necessary, materialize the offset into a register and use
   // the indexed form.  Also handle stack pointers with special needs.
   unsigned IndexReg = 0;
   PPCSimplifyAddress(Addr, UseOffset, IndexReg);
 
+  if (ResultReg == 0)
+    ResultReg = createResultReg(UseRC);
+
   // If this is a potential VSX load with an offset of 0, a VSX indexed load can
   // be used.
   bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
   bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
   bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
-  bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD;
+  bool Is64VSXLoad = IsVSFRC && Opc == PPC::LFD;
   if ((Is32VSXLoad || Is64VSXLoad) &&
       (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
       (Addr.Offset == 0)) {
     UseOffset = false;
   }
 
-  if (ResultReg == 0)
-    ResultReg = createResultReg(UseRC);
-
   // Note: If we still have a frame index here, we know the offset is
   // in range, as otherwise PPCSimplifyAddress would have converted it
   // into a RegBase.
   if (Addr.BaseType == Address::FrameIndexBase) {
     // VSX only provides an indexed load.
     if (Is32VSXLoad || Is64VSXLoad) return false;
 
     MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
switch (Opc) {
       case PPC::LWZ:    Opc = PPC::LWZX;    break;
       case PPC::LWZ8:   Opc = PPC::LWZX8;   break;
       case PPC::LWA:    Opc = PPC::LWAX;    break;
       case PPC::LWA_32: Opc = PPC::LWAX_32; break;
       case PPC::LD:     Opc = PPC::LDX;     break;
       case PPC::LFS:    Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
       case PPC::LFD:    Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
     }
-    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
-      .addReg(Addr.Base.Reg).addReg(IndexReg);
+
+    auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
+           TII.get(Opc), ResultReg);
+
+    // If we have an index register defined we use it in the store inst,
+    // otherwise we use X0 as base as it makes the vector instructions to
+    // use zero in the computation of the effective address regardless the
+    // content of the register.
+    if (IndexReg)
+      MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
+    else
+      MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
   }
 
   return true;
 }
 
 // Attempt to fast-select a load instruction.
 bool PPCFastISel::SelectLoad(const Instruction *I) {
   // FIXME: No atomic loads are supported.
unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
   // No plans to handle long double here.
   if (VT != MVT::f32 && VT != MVT::f64)
     return 0;
 
   // All FP constants are loaded from the constant pool.
   unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
   assert(Align > 0 && "Unexpectedly missing alignment information!");
   unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
-  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
+  const TargetRegisterClass *RC =
+    (VT == MVT::f32) ? &PPC::F4RCRegClass : &PPC::F8RCRegClass;
+  unsigned DestReg = createResultReg(RC);
   CodeModel::Model CModel = TM.getCodeModel();
 
   MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
       MachinePointerInfo::getConstantPool(*FuncInfo.MF),
       MachineMemOperand::MOLoad, (VT == MVT::f32) ? 4 : 8, Align);
 
   unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
   unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);

test/CodeGen/PowerPC/pr28630.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -O0 < %s
+
+define double @test() {
+  ret double 1.000000e+00
+}
+
+@g = common global double 0.000000e+00, align 8
+
+define double @testitd() {
+  %g = load double, double* @g, align 8
+  ret double %g
+}
+