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[X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element
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Authored by RKSimon on Jul 19 2016, 6:13 AM.

Details

Summary

Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW.

But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register.

This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41).

I can commit these separately but included them together for review.

Fix for PR27265.

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 64477.Jul 19 2016, 6:13 AM
RKSimon retitled this revision from to [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th element.
RKSimon updated this object.
RKSimon added reviewers: qcolombet, ab, spatel, andreadb.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
spatel accepted this revision.Jul 20 2016, 8:45 AM
spatel edited edge metadata.

LGTM - one refactoring suggestion inline.

lib/Target/X86/X86ISelLowering.cpp
12531–12545 ↗(On Diff #64477)

Can you pull this chunk (if bitsize == 16 {}) out as a helper function so we don't have 2 copies of it?

This revision is now accepted and ready to land.Jul 20 2016, 8:45 AM
This revision was automatically updated to reflect the committed changes.