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Differential D22375

AMDPU: Use noregister for unset exports
AbandonedPublic

Authored by arsenm on Jul 14 2016, 11:42 AM.

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Reviewers
• tstellarAMD

Diff Detail

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arsenm updated this revision to Diff 64020.Jul 14 2016, 11:42 AM
arsenm retitled this revision from to AMDPU: Use noregister for unset exports.
arsenm updated this object.
arsenm added a reviewer: • tstellarAMD.
arsenm added a subscriber: llvm-commits.
Herald added a subscriber: arsenm. · View Herald TranscriptJul 14 2016, 11:42 AM
• tstellarAMD edited edge metadata.Jul 15 2016, 10:00 AM

What encoding is used for NoRegister?

arsenm added a comment.Jul 15 2016, 10:31 AM
In D22375#485595, @tstellarAMD wrote:

What encoding is used for NoRegister?

0, which is the same as vgpr0 for export so nothing changes there

• tstellarAMD accepted this revision.Jul 15 2016, 1:44 PM
• tstellarAMD edited edge metadata.

LGTM.

This revision is now accepted and ready to land.Jul 15 2016, 1:44 PM
arsenm abandoned this revision.Apr 4 2020, 4:39 PM
Herald added subscribers: kerbowa, nhaehnle, wdng, jvesely. · View Herald TranscriptApr 4 2020, 4:39 PM

Revision Contents

PathSize
lib/
Target/
AMDGPU/
1 line
8 lines

Diff 64020

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Show First 20 Lines • Show All 338 Lines • ▼ Show 20 Lines for (const MachineInstr &MI : MBB) {
unsigned reg = MO.getReg(); unsigned reg = MO.getReg();
switch (reg) { switch (reg) {
case AMDGPU::EXEC: case AMDGPU::EXEC:
case AMDGPU::EXEC_LO: case AMDGPU::EXEC_LO:
case AMDGPU::EXEC_HI: case AMDGPU::EXEC_HI:
case AMDGPU::SCC: case AMDGPU::SCC:
case AMDGPU::M0: case AMDGPU::M0:
case AMDGPU::NoRegister:
continue; continue;
case AMDGPU::VCC: case AMDGPU::VCC:
case AMDGPU::VCC_LO: case AMDGPU::VCC_LO:
case AMDGPU::VCC_HI: case AMDGPU::VCC_HI:
VCCUsed = true; VCCUsed = true;
continue; continue;
▲ Show 20 Lines • Show All 388 Lines • Show Last 20 Lines

lib/Target/AMDGPU/SILowerControlFlow.cpp

Show First 20 Lines • Show All 225 Lines • ▼ Show 20 Lines BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
.addMBB(&NextBB); .addMBB(&NextBB);
MachineBasicBlock::iterator Insert = SkipBB->begin(); MachineBasicBlock::iterator Insert = SkipBB->begin();
// Exec mask is zero: Export to NULL target... // Exec mask is zero: Export to NULL target...
BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE)) BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP_DONE))
.addImm(0x09) // tgt V_008DFC_SQ_EXP_NULL .addImm(0x09) // tgt V_008DFC_SQ_EXP_NULL
.addImm(1) // vm .addImm(1) // vm
.addReg(AMDGPU::VGPR0, RegState::Undef) .addReg(AMDGPU::NoRegister) // src0
.addReg(AMDGPU::VGPR0, RegState::Undef) .addReg(AMDGPU::NoRegister) // src1
.addReg(AMDGPU::VGPR0, RegState::Undef) .addReg(AMDGPU::NoRegister) // src2
.addReg(AMDGPU::VGPR0, RegState::Undef) .addReg(AMDGPU::NoRegister) // src3
.addImm(0) // compr .addImm(0) // compr
.addImm(0); // en .addImm(0); // en
// ... and terminate wavefront. // ... and terminate wavefront.
BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM)); BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
return true; return true;
} }
▲ Show 20 Lines • Show All 594 Lines • Show Last 20 Lines