PowerPC: Use shouldAssumeDSOLocal in classifyGlobalReference

[• rafael]

Summary

And teach shouldAssumeDSOLocal that ppc has no copy relocations.

The resulting code handlen a few more case than before. For example, it
knows that a weak symbol can be resolved to another .o file, but it
will still be in the main executable.

[• rafael]

adding llvm-commits

[• rafael]

ping

[sfertile]

@Rafael Are you still interested in getting this patch reviewed?

[hfinkel]

So you can't interpose weak symbols on PPC?

lib/Target/TargetMachine.cpp

151

We should add a comment here that PPC does not use copy relocations.

[• rafael]

rebase and add comment.

[hfinkel]

LGTM

lib/Target/PowerPC/PPCSubtarget.cpp

bool PPCSubtarget::useAA() const {
   // Use AA during code generation for the embedded cores.
   return needsAggressiveScheduling(DarwinDirective);
 }
 
 bool PPCSubtarget::enableSubRegLiveness() const {
   return UseSubRegLiveness;
 }
 
-unsigned char PPCSubtarget::classifyGlobalReference(
-    const GlobalValue *GV) const {
+unsigned char
+PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const {
   // Note that currently we don't generate non-pic references.
   // If a caller wants that, this will have to be updated.
 
   // Large code model always uses the TOC even for local symbols.
   if (TM.getCodeModel() == CodeModel::Large)
     return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
 
-  unsigned char flags = PPCII::MO_PIC_FLAG;
-
-  // Only if the relocation mode is PIC do we have to worry about
-  // interposition. In all other cases we can use a slightly looser standard to
-  // decide how to access the symbol.
-  if (TM.getRelocationModel() == Reloc::PIC_) {
-    // If it's local, or it's non-default, it can't be interposed.
-    if (!GV->hasLocalLinkage() &&
-        GV->hasDefaultVisibility()) {
-      flags |= PPCII::MO_NLP_FLAG;
-    }
-    return flags;
-  }
-
-  if (GV->isStrongDefinitionForLinker())
-    return flags;
-  return flags | PPCII::MO_NLP_FLAG;
+  if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
+    return PPCII::MO_PIC_FLAG;
+  return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
 }
 
 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }

lib/Target/TargetMachine.cpp

bool TargetMachine::shouldAssumeDSOLocal(const Module &M,
 
   bool IsExecutable =
       RM == Reloc::Static || M.getPIELevel() != PIELevel::Default;
   if (IsExecutable) {
     // If the symbol is defined, it cannot be preempted.
     if (GV && !GV->isDeclarationForLinker())
       return true;
 
-    bool IsTLS = GV && GV->isThreadLocal();
     // Check if we can use copy relocations.
-    if (!IsTLS && (RM == Reloc::Static || CanUseCopyRelocWithPIE))
+    bool IsTLS = GV && GV->isThreadLocal();
+    Triple::ArchType Arch = TT.getArch();
+    bool IsPPC =
+        Arch == Triple::ppc || Arch == Triple::ppc64 || Arch == Triple::ppc64le;
+    if (!IsTLS && !IsPPC && (RM == Reloc::Static || CanUseCopyRelocWithPIE))
       return true;
   }
 
   // ELF supports preemption of other symbols.
   return false;
 }
 
 TLSModel::Model TargetMachine::getTLSModel(const GlobalValue *GV) const {

test/CodeGen/PowerPC/fast-isel-load-store.ll

 }
 
 ;; std requires an offset that fits in 16 bits, so we need stdx here.
 define void @t17(i64 %v) nounwind {
 ; ELF64: t17
   %1 = add nsw i64 %v, 1
   store i64 %1, i64* getelementptr inbounds ([8192 x i64], [8192 x i64]* @i, i32 0, i64 5000), align 8
 ; ELF64: addis
-; ELF64: ld
+; ELF64: addi
 ; ELF64: addi
 ; ELF64: lis
 ; ELF64: ori
 ; ELF64: stdx
   ret void
 }
 

test/CodeGen/PowerPC/mcm-13.ll

-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck --check-prefix=MEDIUM %s
 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck %s
 
 ; Test correct code generation for medium and large code model
 ; for loading and storing a weak variable
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 

 ; CHECK-LABEL: test_weak:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
 ; CHECK: .section .toc
 ; CHECK: .LC[[TOCNUM]]:
 ; CHECK: .tc {{[a-z0-9A-Z_.]+}}[TC],{{[a-z0-9A-Z_.]+}}
+
+; MEDIUM-LABEL: test_weak:
+; MEDIUM: addis [[REG1:[0-9]+]], 2, wi@toc@ha
+; MEDIUM: addi [[REG1]], [[REG1]], wi@toc@l
+; MEDIUM: lwz {{[0-9]+}}, 0([[REG1]])
+; MEDIUM: stw {{[0-9]+}}, 0([[REG1]])

test/CodeGen/PowerPC/mcm-6.ll

-; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -O0 -code-model=medium < %s | FileCheck --check-prefix=MEDIUM %s
 ; RUN: llc -mcpu=pwr7 -O0 -code-model=large < %s | FileCheck %s
 
 ; Test correct code generation for medium and large code model
 ; for loading and storing a tentatively defined variable.
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
 

 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
 ; CHECK: stw {{[0-9]+}}, 0([[REG2]])
 ; CHECK: .section .toc
 ; CHECK: .LC[[TOCNUM]]:
 ; CHECK: .tc [[VAR:[a-z0-9A-Z_.]+]][TC],{{[a-z0-9A-Z_.]+}}
 ; CHECK: .comm [[VAR]],4,4
+
+; MEDIUM-LABEL: test_tentative:
+; MEDIUM: addis [[REG1:[0-9]+]], 2, ti@toc@ha
+; MEDIUM: addi [[REG1]], [[REG1]], ti@toc@l
+; MEDIUM: lwz {{[0-9]+}}, 0([[REG1]])
+; MEDIUM: stw {{[0-9]+}}, 0([[REG1]])
+; MEDIUM: .comm ti,4,4

test/CodeGen/PowerPC/mcm-obj.ll

 define signext i32 @test_tentative() nounwind {
 entry:
   %0 = load i32, i32* @ti, align 4
   %inc = add nsw i32 %0, 1
   store i32 %inc, i32* @ti, align 4
   ret i32 %0
 }
 
-; Verify generation of R_PPC64_TOC16_HA and R_PPC64_TOC16_LO_DS for
-; accessing tentatively declared variable ti.
+; Verify generation of relocations foraccessing variable ti.
 ;
 ; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
-; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
+; MEDIUM-NEXT:     0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO [[SYM6]]
 ;
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_HA [[SYM6:[^ ]+]]
 ; LARGE-NEXT:      0x{{[0-9,A-F]+}} R_PPC64_TOC16_LO_DS [[SYM6]]
 
 define i8* @test_fnaddr() nounwind {
 entry:
   %func = alloca i32 (i32)*, align 8
   store i32 (i32)* @foo, i32 (i32)** %func, align 8

test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

 ; should still trigger for v2f64, producing an lxvdsx.
 ; Function Attrs: nounwind
 define <2 x double> @buildd() #0 {
 entry:
   %0 = load double, double* @d, align 8
   %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0
   %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer
   ret <2 x double> %splat.splat
-; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l
+; CHECK: addi [[REG1:[0-9]+]], [[REG1]], d@toc@l
 ; CHECK: lxvdsx 34, 0, [[REG1]]
-; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l
+; CHECK-LE: addi [[REG1:[0-9]+]], [[REG1]], d@toc@l
 ; CHECK-LE: lxvdsx 34, 0, [[REG1]]
 }
 
 ; Function Attrs: nounwind
 define signext i8 @getsc0(<16 x i8> %vsc) {
 entry:
   %vsc.addr = alloca <16 x i8>, align 16
   store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16

test/CodeGen/PowerPC/ppc64le-aggregates.ll

 entry:
   %0 = load [8 x float], [8 x float]* getelementptr inbounds (%struct.float8, %struct.float8* @g8, i64 0, i32 0), align 4
   %1 = load [5 x float], [5 x float]* getelementptr inbounds (%struct.float5, %struct.float5* @g5, i64 0, i32 0), align 4
   %2 = load [2 x float], [2 x float]* getelementptr inbounds (%struct.float2, %struct.float2* @g2, i64 0, i32 0), align 4
   tail call void @test2([8 x float] %0, [5 x float] %1, [2 x float] %2)
   ret void
 }
 ; CHECK-LABEL: @caller2
-; CHECK: ld {{[0-9]+}}, .LC
+; CHECK: addis {{[0-9]+}}, 2, g2@toc@ha
 ; CHECK-DAG: lfs 1, 0({{[0-9]+}})
 ; CHECK-DAG: lfs 2, 4({{[0-9]+}})
 ; CHECK-DAG: lfs 3, 8({{[0-9]+}})
 ; CHECK-DAG: lfs 4, 12({{[0-9]+}})
 ; CHECK-DAG: lfs 5, 16({{[0-9]+}})
 ; CHECK-DAG: lfs 6, 20({{[0-9]+}})
 ; CHECK-DAG: lfs 7, 24({{[0-9]+}})
 ; CHECK-DAG: lfs 8, 28({{[0-9]+}})

test/CodeGen/PowerPC/ppcf128-endian.ll

-; RUN: llc -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
+; RUN: llc -mcpu=pwr7 -mattr=+altivec -mattr=-vsx -relocation-model=pic < %s | FileCheck %s
 
 target datalayout = "e-m:e-i64:64-n32:64"
 target triple = "powerpc64le-unknown-linux-gnu"
 
 @g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
 
 define void @callee(ppc_fp128 %x) {
 entry: