[ARM, AArch64] Add Rotate Right (ROR) Intrinsic.

[mgrang]

Summary

Here is the LLVM part of this patch:
http://reviews.llvm.org/D21456

[t.p.northover]

I don't think this needs to be an intrinsic, certainly not at the Clang level. We usually try to model things as natural LLVM IR wherever possible. This means that that all front-ends can benefit, rather than just the people using special intrinsics; it also avoids adding yet more portability issues when people use the builtins.

In the case of ROR, there are issues getting perfect CodeGen in the face of larger-than-register rotates. But I don't think they're insurmountable in either the mid- or back-end.

Also: tests! You should almost always include tests in any patch, no matter how trivial it is.

Cheers.

Tim.

[mgrang]

Thanks for your comments Tim.

I have already included two test cases with this patch. I guess I will add some tests with the LLVM part of this patch as well.

The use case for this intrinsic is a customer who makes calls to __builtin_arm_ror in their code base. Currently they compile with ARMCC, but LLVM does not have this intrinsic. So porting the code to build with LLVM becomes a hassle.

To facilitate customers to switch to LLVM we wanted to implement the following intrinsics:

ror: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359125001077.html
enable_irq: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359124996163.html
disable_irq: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359125001077.html
current_sp : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359124995149.html
current_pc : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359124994884.html
breakpoint : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/CJAHBCFH.html

Could you please let me know if this is something that the community would like to support? I can then implement each one of these (although we can work on the implementation details).

Thanks,
Mandeep

[weimingz]

right, __ror is in arm_acle.h ...

Good to know there is such wrapper header file. :)

Thanks,

Weiming

[mgrang]

Thanks Tim for pointing out that __ror is already implemented in arm_acle.h. My patches are no longer needed then.

I will work on implementing the other intrinsics I mentioned earlier.

Thanks,
Mandeep

include/clang/Basic/BuiltinsAArch64.def

 // Memory barrier
 BUILTIN(__builtin_arm_dmb, "vUi", "nc")
 BUILTIN(__builtin_arm_dsb, "vUi", "nc")
 BUILTIN(__builtin_arm_isb, "vUi", "nc")
 
 // Prefetch
 BUILTIN(__builtin_arm_prefetch, "vvC*UiUiUiUi", "nc")
 
+// Rotate Right (ROR)
+BUILTIN(__builtin_arm_ror, "UiUiUi", "n")
+BUILTIN(__builtin_arm_ror64, "LUiLUiLUi", "n")
+
 // System Registers
 BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
 BUILTIN(__builtin_arm_rsr64, "LUicC*", "nc")
 BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
 BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
 BUILTIN(__builtin_arm_wsr64, "vcC*LUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 BUILTIN(__builtin_thread_pointer, "v*", "nc")
 
 #undef BUILTIN

include/clang/Basic/BuiltinsARM.def

 // Data barrier
 BUILTIN(__builtin_arm_dmb, "vUi", "nc")
 BUILTIN(__builtin_arm_dsb, "vUi", "nc")
 BUILTIN(__builtin_arm_isb, "vUi", "nc")
 
 // Prefetch
 BUILTIN(__builtin_arm_prefetch, "vvC*UiUi", "nc")
 
+// Rotate Right (ROR)
+BUILTIN(__builtin_arm_ror, "UiUiUi", "n")
+
 // System registers (ACLE)
 BUILTIN(__builtin_arm_rsr, "UicC*", "nc")
 BUILTIN(__builtin_arm_rsr64, "LLUicC*", "nc")
 BUILTIN(__builtin_arm_rsrp, "v*cC*", "nc")
 BUILTIN(__builtin_arm_wsr, "vcC*Ui", "nc")
 BUILTIN(__builtin_arm_wsr64, "vcC*LLUi", "nc")
 BUILTIN(__builtin_arm_wsrp, "vcC*vC*", "nc")
 

lib/CodeGen/CGBuiltin.cpp

static bool HasExtraNeonArgument(unsigned BuiltinID) {
   return true;
 }
 
 Value *CodeGenFunction::EmitARMBuiltinExpr(unsigned BuiltinID,
                                            const CallExpr *E) {
   if (auto Hint = GetValueForARMHint(BuiltinID))
     return Hint;
 
+  if (BuiltinID == ARM::BI__builtin_arm_ror) {
+    Value *Val   = EmitScalarExpr(E->getArg(0));
+    Value *Shift = EmitScalarExpr(E->getArg(1));
+    Function *F  = CGM.getIntrinsic(Intrinsic::arm_ror);
+    return Builder.CreateCall(F, {Val, Shift});
+  }
+
   if (BuiltinID == ARM::BI__emit) {
     bool IsThumb = getTarget().getTriple().getArch() == llvm::Triple::thumb;
     llvm::FunctionType *FTy =
         llvm::FunctionType::get(VoidTy, /*Variadic=*/false);
 
     APSInt Value;
     if (!E->getArg(0)->EvaluateAsInt(Value, CGM.getContext()))
       llvm_unreachable("Sema will ensure that the parameter is constant");
case AArch64::BI__builtin_arm_sevl:
     break;
   }
 
   if (HintID != static_cast<unsigned>(-1)) {
     Function *F = CGM.getIntrinsic(Intrinsic::aarch64_hint);
     return Builder.CreateCall(F, llvm::ConstantInt::get(Int32Ty, HintID));
   }
 
+  if (BuiltinID == AArch64::BI__builtin_arm_ror ||
+      BuiltinID == AArch64::BI__builtin_arm_ror64) {
+    Value *Val   = EmitScalarExpr(E->getArg(0));
+    Value *Shift = EmitScalarExpr(E->getArg(1));
+    Function *F  = CGM.getIntrinsic(Intrinsic::aarch64_ror, Val->getType());
+    return Builder.CreateCall(F, {Val, Shift});
+  }
+
   if (BuiltinID == AArch64::BI__builtin_arm_prefetch) {
     Value *Address         = EmitScalarExpr(E->getArg(0));
     Value *RW              = EmitScalarExpr(E->getArg(1));
     Value *CacheLevel      = EmitScalarExpr(E->getArg(2));
     Value *RetentionPolicy = EmitScalarExpr(E->getArg(3));
     Value *IsData          = EmitScalarExpr(E->getArg(4));
 
     Value *Locality = nullptr;

test/CodeGen/builtins-arm.c

 }
 
 // CHECK: call {{.*}} @llvm.arm.rbit(i32 %a)
 
 unsigned rbit(unsigned a) {
   return __builtin_arm_rbit(a);
 }
 
+// CHECK: call {{.*}} @llvm.arm.ror(i32 %a, i32 %b)
+
+unsigned ror(unsigned a, unsigned b) {
+  return __builtin_arm_ror(a, b);
+}
+
 void prefetch(int i) {
   __builtin_arm_prefetch(&i, 0, 1);
 // CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 0, i32 3, i32 1)
 
   __builtin_arm_prefetch(&i, 1, 1);
 // CHECK: call {{.*}} @llvm.prefetch(i8* %{{.*}}, i32 1, i32 3, i32 1)
 
 

test/CodeGen/builtins-arm64.c

unsigned rbit(unsigned a) {
   return __builtin_arm_rbit(a);
 }
 
 // CHECK: call {{.*}} @llvm.aarch64.rbit.i64(i64 %a)
 unsigned long long rbit64(unsigned long long a) {
   return __builtin_arm_rbit64(a);
 }
 
+// CHECK: call {{.*}} @llvm.aarch64.ror.i32(i32 %a, i32 %b)
+unsigned ror(unsigned a, unsigned b) {
+  return __builtin_arm_ror(a, b);
+}
+
+// CHECK: call {{.*}} @llvm.aarch64.ror.i64(i64 %a, i64 %b)
+unsigned long long ror64(unsigned long long a, unsigned long long b) {
+  return __builtin_arm_ror64(a, b);
+}
+
 void hints() {
   __builtin_arm_nop();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0)
   __builtin_arm_yield();  //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1)
   __builtin_arm_wfe();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2)
   __builtin_arm_wfi();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 3)
   __builtin_arm_sev();    //CHECK: call {{.*}} @llvm.aarch64.hint(i32 4)
   __builtin_arm_sevl();   //CHECK: call {{.*}} @llvm.aarch64.hint(i32 5)
 }