[ARM, AArch64] Add Rotate Right (ROR) Intrinsic.

[mgrang]

Summary

Here is the Clang part of this patch:
http://reviews.llvm.org/D21457

[jmolloy]

Hi,

I'm not sure I understand why we need this. Doesn't normal bit-twiddling in C select the right instruction?

James

[mgrang]

Hi James,

(copying over my response from the Clang part of this patch)

The use case for this intrinsic is a customer who makes calls to __builtin_arm_ror in their code base. Currently they compile with ARMCC, but LLVM does not have this intrinsic. So porting the code to build with LLVM becomes a hassle.

To facilitate customers to switch to LLVM we wanted to implement the following intrinsics:

ror: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359125001077.html
enable_irq: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359124996163.html
disable_irq: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359125001077.html
current_sp : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359124995149.html
current_pc : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0472m/chr1359124994884.html
breakpoint : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0491c/CJAHBCFH.html

Could you please let me know if this is something that the community would like to support? I can then implement each one of these (although we can work on the implementation details).

Thanks,
Mandeep

include/llvm/IR/IntrinsicsAArch64.td

def int_aarch64_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
     [IntrNoMem]>;
 def int_aarch64_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
     [IntrNoMem]>;
 def int_aarch64_crc32x  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
     [IntrNoMem]>;
 def int_aarch64_crc32cx : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i64_ty],
     [IntrNoMem]>;
 }
+
+// Rotate Right (ROR)
+def int_aarch64_ror : Intrinsic<[llvm_anyint_ty],
+                                [LLVMMatchType<0>, LLVMMatchType<0>],
+                                [IntrNoMem]>;

include/llvm/IR/IntrinsicsARM.td

 def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
 def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
 def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
 def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
 def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
 def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
 def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
 
+
+// Rotate Right (ROR)
+def int_arm_ror : Intrinsic<[llvm_i32_ty],
+                            [llvm_i32_ty, llvm_i32_ty],
+                            [IntrNoMem]>;
+
 } // end TargetPrefix

lib/Target/AArch64/AArch64InstrInfo.td

 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
 def : ShiftAlias<"rorv", RORVWr, GPR32>;
 def : ShiftAlias<"rorv", RORVXr, GPR64>;
 
+// Rotate Right (ROR)
+def : Pat<(int_aarch64_ror GPR32:$Rn, GPR32:$Rm), (RORVWr $Rn, $Rm)>;
+def : Pat<(int_aarch64_ror GPR64:$Rn, GPR64:$Rm), (RORVXr $Rn, $Rm)>;
+
 // Multiply-add
 let AddedComplexity = 7 in {
 defm MADD : MulAccum<0, "madd", add>;
 defm MSUB : MulAccum<1, "msub", sub>;
 
 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
           (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),

lib/Target/ARM/ARMISelLowering.cpp

ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
   SDLoc dl(Op);
   switch (IntNo) {
   default: return SDValue();    // Don't custom lower most intrinsics.
   case Intrinsic::arm_rbit: {
     assert(Op.getOperand(1).getValueType() == MVT::i32 &&
            "RBIT intrinsic must have i32 type!");
     return DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, Op.getOperand(1));
   }
+  case Intrinsic::arm_ror: {
+    assert(Op.getOperand(1).getValueType() == MVT::i32 &&
+           Op.getOperand(2).getValueType() == MVT::i32 &&
+           "ROR intrinsic must have both operands of i32 type!");
+    return DAG.getNode(ISD::ROTR, dl, MVT::i32,
+                       Op.getOperand(1), Op.getOperand(2));
+  }
   case Intrinsic::thread_pointer: {
     EVT PtrVT = getPointerTy(DAG.getDataLayout());
     return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
   }
   case Intrinsic::eh_sjlj_lsda: {
     MachineFunction &MF = DAG.getMachineFunction();
     ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
     unsigned ARMPCLabelIndex = AFI->createPICLabelUId();