AMDGPU: Emit R_AMDGPU_ABS32_{HI,LO} for scratch buffer relocations

[kzhuravl]

include/llvm/Object/RelocVisitor.h

144–146 ↗

(On Diff #60885)

This processes HI relocations as LO. Should not LO and HI be processed differently, or am I missing something?

[• tstellarAMD]

include/llvm/Object/RelocVisitor.h

144–146 ↗

(On Diff #60885)

The RelocVisitor seems to only be used in DwarfContext.cpp. It's not clear me what it's even supposed to do with absolute relocations. Is this code even necessary?

[kzhuravl]

include/llvm/Object/RelocVisitor.h

144–146 ↗

(On Diff #60885)

I think at this point we will only need to handle R_AMDGPU_ABS32 in RelocVisitor, since we are going to use it for dwarf relocs

[• tstellarAMD]

Split changes outside of lib/Target/AMDGPU into a new patch: http://reviews.llvm.org/D21443

[• rafael]

test/CodeGen/AMDGPU/large-alloca-compute.ll

5

Why do you need to use "llc -filetype=obj"?

Please split this into tow tests. One prints assembly and checks it.
Another parses assembly and checks the relocations.

[• tstellarAMD]

Split the test case in to to avoid using llc -filetype=obj

[• rafael]

Lgtm, but I have a question:

Will SCRATCH_RSRC_DWORD also need special treatment in the linker? If so
we should have special relocations for it to avoid using names in the
linker. This is similar to how the got position is accessed: magical name
for the assembler, different relocation for the linker.

Cheers,
Rafael

[• tstellarAMD]

In D21400#461541, @rafael wrote:

Lgtm, but I have a question:

Will SCRATCH_RSRC_DWORD also need special treatment in the linker? If so
we should have special relocations for it to avoid using names in the
linker. This is similar to how the got position is accessed: magical name
for the assembler, different relocation for the linker.

This won't need any special handling in the linker. This is only used by our legacy path which does not use lld at all.

[• rafael]

Cool, LGTM.

[kzhuravl]

LGTM

lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

 
 namespace {
 
 class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   AMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend);
 protected:
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
-                        const MCFixup &Fixup, bool IsPCRel) const override {
-    return Fixup.getKind();
-  }
-
+                        const MCFixup &Fixup, bool IsPCRel) const override;
 };
 
 
 } // End anonymous namespace
 
 AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit,
                                              bool HasRelocationAddend)
   : MCELFObjectTargetWriter(Is64Bit,
                             ELF::ELFOSABI_AMDGPU_HSA,
                             ELF::EM_AMDGPU,
                             HasRelocationAddend) { }
 
+unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
+                                             const MCValue &Target,
+                                             const MCFixup &Fixup,
+                                             bool IsPCRel) const {
+  // SCRATCH_RSRC_DWORD[01] is a special global variable that represents
+  // the scratch buffer.
+  if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD0")
+    return ELF::R_AMDGPU_ABS32_LO;
+  if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
+    return ELF::R_AMDGPU_ABS32_HI;
+
+  llvm_unreachable("unhandled relocation type");
+}
+
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit,
                                                   bool HasRelocationAddend,
                                                   raw_pwrite_stream &OS) {
   MCELFObjectTargetWriter *MOTW =
       new AMDGPUELFObjectWriter(Is64Bit, HasRelocationAddend);
   return createELFObjectWriter(MOTW, OS, true);
 }

test/CodeGen/AMDGPU/large-alloca-compute.ll

 ; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
 
 ; FIXME: align on alloca seems to be ignored for private_segment_alignment
 
 ; ALL-LABEL: {{^}}large_alloca_compute_shader:
 
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
-; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0, kind: FK_Data_4
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
-; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1, kind: FK_Data_4
+; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000
 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000
 
 
 ; GCNHSA: .amd_kernel_code_t
 
 ; GCNHSA: compute_pgm_rsrc2_scratch_en = 1

test/MC/AMDGPU/reloc.s

+// RUN: llvm-mc -filetype=obj -triple amdgcn-- -mcpu=kaveri -show-encoding %s | llvm-readobj -relocations | FileCheck %s
+
+// CHECK: Relocations [
+// CHECK: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
+// CHECK: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
+// CHECK: ]
+
+kernel:
+  s_mov_b32 s0, SCRATCH_RSRC_DWORD0
+  s_mov_b32 s1, SCRATCH_RSRC_DWORD1
+
+.globl SCRATCH_RSRC_DWORD0