AMDGPU: Emit R_AMDGPU_ABS32_{HI,LO} for scratch buffer relocations

[kzhuravl]

include/llvm/Object/RelocVisitor.h

144–146

This processes HI relocations as LO. Should not LO and HI be processed differently, or am I missing something?

[• tstellarAMD]

include/llvm/Object/RelocVisitor.h

144–146

The RelocVisitor seems to only be used in DwarfContext.cpp. It's not clear me what it's even supposed to do with absolute relocations. Is this code even necessary?

[kzhuravl]

include/llvm/Object/RelocVisitor.h

144–146

I think at this point we will only need to handle R_AMDGPU_ABS32 in RelocVisitor, since we are going to use it for dwarf relocs

[• tstellarAMD]

Split changes outside of lib/Target/AMDGPU into a new patch: http://reviews.llvm.org/D21443

[• rafael]

test/CodeGen/AMDGPU/large-alloca-compute.ll

5

Why do you need to use "llc -filetype=obj"?

Please split this into tow tests. One prints assembly and checks it.
Another parses assembly and checks the relocations.

[• tstellarAMD]

Split the test case in to to avoid using llc -filetype=obj

[• rafael]

Lgtm, but I have a question:

Will SCRATCH_RSRC_DWORD also need special treatment in the linker? If so
we should have special relocations for it to avoid using names in the
linker. This is similar to how the got position is accessed: magical name
for the assembler, different relocation for the linker.

Cheers,
Rafael

[• tstellarAMD]

In D21400#461541, @rafael wrote:

Lgtm, but I have a question:

Will SCRATCH_RSRC_DWORD also need special treatment in the linker? If so
we should have special relocations for it to avoid using names in the
linker. This is similar to how the got position is accessed: magical name
for the assembler, different relocation for the linker.

This won't need any special handling in the linker. This is only used by our legacy path which does not use lld at all.

[• rafael]

Cool, LGTM.

[kzhuravl]

LGTM

include/llvm/Object/RelocVisitor.h

if (ObjToVisit.getBytesInAddress() == 8) { // 64-bit object file
           return visitELF_SPARCV9_32(R, Value);
         case llvm::ELF::R_SPARC_64:
         case llvm::ELF::R_SPARC_UA64:
           return visitELF_SPARCV9_64(R, Value);
         default:
           HasError = true;
           return RelocToApply();
         }
+      case Triple::amdgcn:
+        switch (RelocType) {
+        case llvm::ELF::R_AMDGPU_ABS32_LO:
+        case llvm::ELF::R_AMDGPU_ABS32_HI:
+          return visitELF_AMDGPU_32(R, Value);
+        default:
+          HasError = true;
+          return RelocToApply();
+        }
+
       default:
         HasError = true;
         return RelocToApply();
       }
     } else if (ObjToVisit.getBytesInAddress() == 4) { // 32-bit object file
       switch (ObjToVisit.getArch()) {
       case Triple::x86:
         switch (RelocType) {
RelocToApply visitELF_ARM_ABS32(RelocationRef R, uint64_t Value) {
 
     // Overflow check allows for both signed and unsigned interpretation.
     if (Res < INT32_MIN || Res > UINT32_MAX)
       HasError = true;
 
     return RelocToApply(static_cast<uint32_t>(Res), 4);
   }
 
+  // AMDGPU ELF
+  RelocToApply visitELF_AMDGPU_32(RelocationRef R, uint64_t Value) {
+    int64_t Addend = getELFAddend(R);
+    return RelocToApply(Value + Addend, 4);
+  }
+
   /// I386 COFF
   RelocToApply visitCOFF_I386_SECREL(RelocationRef R, uint64_t Value) {
     return RelocToApply(static_cast<uint32_t>(Value), /*Width=*/4);
   }
 
   RelocToApply visitCOFF_I386_DIR32(RelocationRef R, uint64_t Value) {
     return RelocToApply(static_cast<uint32_t>(Value), /*Width=*/4);
   }

include/llvm/Support/ELF.h

 #include "ELFRelocs/Sparc.def"
 };
 
 // ELF Relocation types for WebAssembly
 enum {
 #include "ELFRelocs/WebAssembly.def"
 };
 
+// ELF Relocation types for AMDGPU
+enum {
+#include "ELFRelocs/AMDGPU.def"
+};
+
 #undef ELF_RELOC
 
 // Section header.
 struct Elf32_Shdr {
   Elf32_Word sh_name;      // Section name (index into string table)
   Elf32_Word sh_type;      // Section type (SHT_*)
   Elf32_Word sh_flags;     // Section flags (SHF_*)
   Elf32_Addr sh_addr;      // Address where section is to be loaded

include/llvm/Support/ELFRelocs/AMDGPU.def

+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_AMDGPU_NONE,          0)
+ELF_RELOC(R_AMDGPU_ABS32_LO,      1)
+ELF_RELOC(R_AMDGPU_ABS32_HI,      2)

lib/Object/ELF.cpp

#include "llvm/Support/ELFRelocs/Sparc.def"
     break;
   case ELF::EM_WEBASSEMBLY:
     switch (Type) {
 #include "llvm/Support/ELFRelocs/WebAssembly.def"
     default:
       break;
     }
     break;
+  case ELF::EM_AMDGPU:
+    switch (Type) {
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    default:
+      break;
+    }
+    break;
   default:
     break;
   }
   return "Unknown";
 }
 
 #undef ELF_RELOC
 
 } // end namespace object
 } // end namespace llvm

lib/ObjectYAML/ELFYAML.cpp

 #include "llvm/Support/ELFRelocs/AArch64.def"
     break;
   case ELF::EM_ARM:
 #include "llvm/Support/ELFRelocs/ARM.def"
     break;
   case ELF::EM_LANAI:
 #include "llvm/Support/ELFRelocs/Lanai.def"
     break;
+  case ELF::EM_AMDGPU:
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    break;
   default:
     llvm_unreachable("Unsupported architecture");
   }
 #undef ELF_RELOC
 }
 
 void ScalarEnumerationTraits<ELFYAML::MIPS_AFL_REG>::enumeration(
     IO &IO, ELFYAML::MIPS_AFL_REG &Value) {

lib/Target/AMDGPU/MCTargetDesc/AMDGPUELFObjectWriter.cpp

 
 namespace {
 
 class AMDGPUELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   AMDGPUELFObjectWriter(bool Is64Bit, bool HasRelocationAddend);
 protected:
   unsigned getRelocType(MCContext &Ctx, const MCValue &Target,
-                        const MCFixup &Fixup, bool IsPCRel) const override {
-    return Fixup.getKind();
-  }
-
+                        const MCFixup &Fixup, bool IsPCRel) const override;
 };
 
 
 } // End anonymous namespace
 
 AMDGPUELFObjectWriter::AMDGPUELFObjectWriter(bool Is64Bit,
                                              bool HasRelocationAddend)
   : MCELFObjectTargetWriter(Is64Bit,
                             ELF::ELFOSABI_AMDGPU_HSA,
                             ELF::EM_AMDGPU,
                             HasRelocationAddend) { }
 
+unsigned AMDGPUELFObjectWriter::getRelocType(MCContext &Ctx,
+                                             const MCValue &Target,
+                                             const MCFixup &Fixup,
+                                             bool IsPCRel) const {
+  switch (Fixup.getKind()) {
+  default: break;
+  case FK_Data_4:
+    // SCRATCH_RSRC_DWORD[01] is a special global variable that represents
+    // the scratch buffer.
+    if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD0")
+      return ELF::R_AMDGPU_ABS32_LO;
+    if (Target.getSymA()->getSymbol().getName() == "SCRATCH_RSRC_DWORD1")
+      return ELF::R_AMDGPU_ABS32_HI;
+  }
+
+  llvm_unreachable("unhandled relocation type");
+}
+
 
 MCObjectWriter *llvm::createAMDGPUELFObjectWriter(bool Is64Bit,
                                                   bool HasRelocationAddend,
                                                   raw_pwrite_stream &OS) {
   MCELFObjectTargetWriter *MOTW =
       new AMDGPUELFObjectWriter(Is64Bit, HasRelocationAddend);
   return createELFObjectWriter(MOTW, OS, true);
 }

test/CodeGen/AMDGPU/large-alloca-compute.ll

 ; RUN: llc -march=amdgcn -mcpu=bonaire -show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=carrizo --show-mc-encoding < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=bonaire -mtriple=amdgcn-unknown-amdhsa < %s -mattr=-flat-for-global | FileCheck -check-prefix=GCNHSA -check-prefix=CIHSA -check-prefix=ALL %s
 ; RUN: llc -march=amdgcn -mcpu=carrizo -mtriple=amdgcn-unknown-amdhsa -mattr=-flat-for-global < %s | FileCheck -check-prefix=GCNHSA -check-prefix=VIHSA -check-prefix=ALL %s
+; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs -filetype=obj | llvm-readobj -relocations | FileCheck --check-prefix=ELF %s
 
 ; FIXME: align on alloca seems to be ignored for private_segment_alignment
 
+; ELF: Relocations [
+; ELF:  .rel.text {
+; ELF: R_AMDGPU_ABS32_LO SCRATCH_RSRC_DWORD0 0x0
+; ELF: R_AMDGPU_ABS32_HI SCRATCH_RSRC_DWORD1 0x0
+; ELF:  }
+; ELF: ]
+
 ; ALL-LABEL: {{^}}large_alloca_compute_shader:
 
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD0, kind: FK_Data_4
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
 ; GCN-DAG: ; fixup A - offset: 4, value: SCRATCH_RSRC_DWORD1, kind: FK_Data_4
 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000