Support/ELF: Add AMDGPU relocation definitions to match documentation

[• tstellarAMD]

These are the non-codegen parts of D21400 and D21401 split out into a separate patch. I also dropped the RelocVisitor changes, because I was using the wrong kinds of relocations for DWARF. These changes will be re-visited when we do more work on DWARF support.

[kzhuravl]

Can you add a test? something along these lines:
http://reviews.llvm.org/file/data/lxwxdp2mphkmmbhdplym/PHID-FILE-z7hdaz3x2zhor57rst56/test_Object_AMDGPU_elf64-relocs.yaml

for each relocation.

[• tstellarAMD]

Add yaml test case.

[kzhuravl]

LGTM

[• rafael]

LGTM too

llvm/trunk/include/llvm/Support/ELF.h

 #include "ELFRelocs/Sparc.def"
 };
 
 // ELF Relocation types for WebAssembly
 enum {
 #include "ELFRelocs/WebAssembly.def"
 };
 
+// ELF Relocation types for AMDGPU
+enum {
+#include "ELFRelocs/AMDGPU.def"
+};
+
 #undef ELF_RELOC
 
 // Section header.
 struct Elf32_Shdr {
   Elf32_Word sh_name;      // Section name (index into string table)
   Elf32_Word sh_type;      // Section type (SHT_*)
   Elf32_Word sh_flags;     // Section flags (SHF_*)
   Elf32_Addr sh_addr;      // Address where section is to be loaded

llvm/trunk/include/llvm/Support/ELFRelocs/AMDGPU.def

+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_AMDGPU_NONE,          0)
+ELF_RELOC(R_AMDGPU_ABS32_LO,      1)
+ELF_RELOC(R_AMDGPU_ABS32_HI,      2)
+ELF_RELOC(R_AMDGPU_ABS64,         3)
+ELF_RELOC(R_AMDGPU_REL32,         4)
+ELF_RELOC(R_AMDGPU_REL64,         5)
+ELF_RELOC(R_AMDGPU_ABS32,         6)

llvm/trunk/lib/Object/ELF.cpp

#include "llvm/Support/ELFRelocs/Sparc.def"
     break;
   case ELF::EM_WEBASSEMBLY:
     switch (Type) {
 #include "llvm/Support/ELFRelocs/WebAssembly.def"
     default:
       break;
     }
     break;
+  case ELF::EM_AMDGPU:
+    switch (Type) {
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    default:
+      break;
+    }
+    break;
   default:
     break;
   }
   return "Unknown";
 }
 
 #undef ELF_RELOC
 
 } // end namespace object
 } // end namespace llvm

llvm/trunk/lib/ObjectYAML/ELFYAML.cpp

 #include "llvm/Support/ELFRelocs/AArch64.def"
     break;
   case ELF::EM_ARM:
 #include "llvm/Support/ELFRelocs/ARM.def"
     break;
   case ELF::EM_LANAI:
 #include "llvm/Support/ELFRelocs/Lanai.def"
     break;
+  case ELF::EM_AMDGPU:
+#include "llvm/Support/ELFRelocs/AMDGPU.def"
+    break;
   default:
     llvm_unreachable("Unsupported architecture");
   }
 #undef ELF_RELOC
 }
 
 void ScalarEnumerationTraits<ELFYAML::MIPS_AFL_REG>::enumeration(
     IO &IO, ELFYAML::MIPS_AFL_REG &Value) {

llvm/trunk/test/Object/AMDGPU/elf64-relocs.yaml

+# RUN: yaml2obj -format=elf %s > %t
+# RUN: llvm-readobj -r %t | FileCheck %s
+
+# CHECK: Relocations [
+# CHECK:   Section (2) .rela.text {
+# CHECK:     0x0 R_AMDGPU_NONE main 0x0
+# CHECK:     0x8 R_AMDGPU_ABS32_LO - 0x0
+# CHECK:     0x10 R_AMDGPU_ABS32_HI - 0x0
+# CHECK:     0x18 R_AMDGPU_ABS64 - 0x0
+# CHECK:     0x20 R_AMDGPU_REL32 - 0x0
+# CHECK:     0x28 R_AMDGPU_REL64 - 0x0
+# CHECK:     0x30 R_AMDGPU_ABS32 - 0x0
+# CHECK:   }
+# CHECK: ]
+
+FileHeader:
+  Class:           ELFCLASS64
+  Data:            ELFDATA2LSB
+  Type:            ET_REL
+  Machine:         EM_AMDGPU
+Sections:
+  - Type:            SHT_PROGBITS
+    Name:            .text
+    Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
+    AddressAlign:    0x08
+    Content:         0000000000000000
+  - Type:            SHT_RELA
+    Name:            .rela.text
+    Link:            .symtab
+    Info:            .text
+    AddressAlign:    0x08
+    Relocations:
+      - Offset:          0x0
+        Symbol:          main
+        Type:            R_AMDGPU_NONE
+      - Offset:          0x8
+        Symbol:          a
+        Type:            R_AMDGPU_ABS32_LO
+      - Offset:          0x10
+        Symbol:          b
+        Type:            R_AMDGPU_ABS32_HI
+      - Offset:          0x18
+        Symbol:          c
+        Type:            R_AMDGPU_ABS64
+      - Offset:          0x20
+        Symbol:          d
+        Type:            R_AMDGPU_REL32
+      - Offset:          0x28
+        Symbol:          e
+        Type:            R_AMDGPU_REL64
+      - Offset:          0x30
+        Symbol:          f
+        Type:            R_AMDGPU_ABS32
+
+Symbols:
+  Local:
+    - Name:            .text
+      Type:            STT_SECTION
+      Section:         .text
+
+  Global:
+    - Name:            main
+      Type:            STT_FUNC
+      Section:         .text
+      Size:            0x08