[X86]: Quit promoting 8 and 16 bit compares to 32 bit.

[kbsmith1]

Summary

This change effectively just reverts r195496, and updates the tests as needed.
8 and 16 bit compares no longer promoted up into 32 bit compares. This has some
nice performance improvements, especially in eembc/rgbcmykv2. In order for this
not to cause performance regressions in 401.bzip2, changes http://reviews.llvm.org/D21085
are also necessary to get all the necessary movb and movw instructions promoted to
movzbl/movzwl.

[echristo]

We talked about this on the list, but getting an explicit ack from Jim.

-eric

[eli.friedman]

test/CodeGen/X86/memcmp.ll

44

16-bit immediate operands are bad for performance on modern x86.

[kbsmith1]

test/CodeGen/X86/memcmp.ll

44

I'm looking into changing the code so that 16 bit compares which have a constant operand will continue to get promoted, and how that affects the performance numbers.

[kbsmith1]

Updated changes so this will continue to promote 16 bit compares to 32 bits if one of the compare
operands is a constant. This addresses Eli Friedman's comment.

[danielcdh]

In D21144#453975, @kbsmith1 wrote:

Updated changes so this will continue to promote 16 bit compares to 32 bits if one of the compare
operands is a constant. This addresses Eli Friedman's comment.

Yes, 16bit immediate constant may introduce LCP that may end up hurting performance. But on newer architectures (sandybridge and later), this problem is much less severe, especially when the loop body fits in LSD. I don't think it's a good idea to blindly convert all 16bit immediate constant comparison to 32bit.

lib/Target/X86/X86ISelLowering.cpp

 
   if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
        Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
-    // Do the comparison at i32 if it's smaller, besides the Atom case.
-    // This avoids subregister aliasing issues. Keep the smaller reference
-    // if we're optimizing for size, however, as that'll allow better folding
-    // of memory operations.
-    if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&
+    // Only promote the compare up to I32 if it is a 16 bit operation
+    // with an immediate.  16 bit immediates are to be avoided.
+    if ((Op0.getValueType() == MVT::i16 &&
+         (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
         !DAG.getMachineFunction().getFunction()->optForMinSize() &&
         !Subtarget.isAtom()) {
       unsigned ExtendOp =

test/CodeGen/X86/3addr-16bit.ll

 
 ; 64BIT-LABEL:     t1:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal 1(%rsi), %eax
+; 64BIT:     movl %esi, %eax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   %1 = add i16 %k, 1                              ; <i16> [#uses=3]
   br i1 %0, label %bb, label %bb1

 
 ; 64BIT-LABEL:     t2:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal -1(%rsi), %eax
+; 64BIT:     movl %esi, %eax
 ; 64BIT:     movzwl %ax
   %0 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   %1 = add i16 %k, -1                             ; <i16> [#uses=3]

 
 ; 64BIT-LABEL:     t3:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal 2(%rsi), %eax
+; 64BIT:     movl %esi, %eax
   %0 = add i16 %k, 2                              ; <i16> [#uses=3]
   %1 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1

 
 ; 64BIT-LABEL:     t4:
 ; 64BIT-NOT: movw %si, %ax
-; 64BIT:     leal (%rsi,%rdi), %eax
+; 64BIT:     movl %esi, %eax
   %0 = add i16 %k, %c                             ; <i16> [#uses=3]
   %1 = icmp eq i16 %k, %c                         ; <i1> [#uses=1]
   br i1 %1, label %bb, label %bb1

test/CodeGen/X86/atomic16.ll

 }
 
 define void @atomic_fetch_max16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_max16
+; X32-LABEL:   atomic_fetch_max16
   %t1 = atomicrmw max  i16* @sc16, i16 %x acquire
-; X64:       movswl
-; X64:       movswl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movswl
-; X32:       movswl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw

 }
 
 define void @atomic_fetch_min16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_min16
+; X32-LABEL:   atomic_fetch_min16
   %t1 = atomicrmw min  i16* @sc16, i16 %x acquire
-; X64:       movswl
-; X64:       movswl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movswl
-; X32:       movswl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw

 }
 
 define void @atomic_fetch_umax16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_umax16
+; X32-LABEL:   atomic_fetch_umax16
   %t1 = atomicrmw umax i16* @sc16, i16 %x acquire
-; X64:       movzwl
-; X64:       movzwl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movzwl
-; X32:       movzwl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw

 }
 
 define void @atomic_fetch_umin16(i16 %x) nounwind {
+; X64-LABEL:   atomic_fetch_umin16
+; X32-LABEL:   atomic_fetch_umin16
   %t1 = atomicrmw umin i16* @sc16, i16 %x acquire
-; X64:       movzwl
-; X64:       movzwl
-; X64:       subl
+; X64:       movw
+; X64:       movw
+; X64:       subw
 ; X64:       cmov
 ; X64:       lock
 ; X64:       cmpxchgw
 
-; X32:       movzwl
-; X32:       movzwl
-; X32:       subl
+; X32:       movw
+; X32:       movw
+; X32:       subw
 ; X32:       cmov
 ; X32:       lock
 ; X32:       cmpxchgw

test/CodeGen/X86/atomic8.ll

 ; X64-LABEL:   atomic_fetch_max8:
 ; X32-LABEL:   atomic_fetch_max8:
   %t1 = atomicrmw max  i8* @sc8, i8 %x acquire
-; X64:       movsbl
-; X64:       movsbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movsbl
-; X32:       movsbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void

 ; X64-LABEL:   atomic_fetch_min8:
 ; X32-LABEL:   atomic_fetch_min8:
   %t1 = atomicrmw min  i8* @sc8, i8 %x acquire
-; X64:       movsbl
-; X64:       movsbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movsbl
-; X32:       movsbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void

 ; X64-LABEL:   atomic_fetch_umax8:
 ; X32-LABEL:   atomic_fetch_umax8:
   %t1 = atomicrmw umax i8* @sc8, i8 %x acquire
-; X64:       movzbl
-; X64:       movzbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movzbl
-; X32:       movzbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void

 ; X64-LABEL:   atomic_fetch_umin8:
 ; X32-LABEL:   atomic_fetch_umin8:
   %t1 = atomicrmw umin i8* @sc8, i8 %x acquire
-; X64:       movzbl
-; X64:       movzbl
-; X64:       subl
+; X64:       movb
+; X64:       movb
+; X64:       subb
 ; X64:       lock
 ; X64:       cmpxchgb
 
-; X32:       movzbl
-; X32:       movzbl
-; X32:       subl
+; X32:       movb
+; X32:       movb
+; X32:       subb
 ; X32:       lock
 ; X32:       cmpxchgb
   ret void

test/CodeGen/X86/ctpop-combine.ll

   %conv = zext i1 %cmp to i32
   ret i32 %conv
 ; CHECK-LABEL: test3:
-; CHECK: cmpl $2
+; CHECK: cmpb $2
 ; CHECK: ret
 }

test/CodeGen/X86/machine-sink-and-implicit-null-checks.ll

 ; CHECK-NEXT:        .byte   1
 ; CHECK-NEXT:        .byte   0
 ; CHECK-NEXT:        .short  0
-; CHECK-NEXT:        .long   2
+; CHECK-NEXT:        .long   1
 
 ; FunctionInfo[0] =
 

test/CodeGen/X86/memcmp.ll

   ret void
 ; CHECK-LABEL: memcmp2:
 ; CHECK: movzwl
-; CHECK-NEXT: movzwl
-; CHECK-NEXT: cmpl
+; CHECK-NEXT: cmpw
 ; NOBUILTIN-LABEL: memcmp2:
 ; NOBUILTIN: callq
 }

test/CodeGen/X86/pr5145.ll

 ; CHECK: atomic_maxmin_i8
   %1 = atomicrmw max  i8* @sc8, i8 5 acquire
 ; CHECK: [[LABEL1:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movsbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: jg
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL1]]
   %2 = atomicrmw min  i8* @sc8, i8 6 acquire
 ; CHECK: [[LABEL3:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movsbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: jl
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL3]]
   %3 = atomicrmw umax i8* @sc8, i8 7 acquire
 ; CHECK: [[LABEL5:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movzbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: ja
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL5]]
   %4 = atomicrmw umin i8* @sc8, i8 8 acquire
 ; CHECK: [[LABEL7:\.?LBB[0-9]+_[0-9]+]]:
-; CHECK: movzbl
-; CHECK: cmpl
+; CHECK: cmpb
+; CHECK: jb
 ; CHECK: lock cmpxchgb
 ; CHECK: jne [[LABEL7]]
   ret void